Microprocessor 1971 Build Instruction Decoder Silicon Gate Logic

# Build the Instruction Decoder From Gates Already Established: Turn a Stored Bit Pattern Into Control

## 1. Separate the Operation Code From the Operand or Register Selection

Once the Intel 4004 captures an instruction, the bit pattern must be translated into actions inside the processor. Its basic instruction byte is divided into two four-bit fields: the upper field, OPR, identifies a broad operation family; the lower field, OPA, refines that choice by selecting a register, condition, or sub-operation. Some instructions use a second byte for immediate data or an address, but the first byte still begins the classification.

$$I_7I_6I_5I_4=\mathrm{OPR}, \qquad I_3I_2I_1I_0=\mathrm{OPA}$$

The decoder is not a memory full of miniature procedures. It is a network of logic gates that recognizes combinations of captured instruction bits. A particular decode line becomes active only when the required ones and zeros are present. For an illustrative four-bit pattern $1010_2$, its recognition term is

$$D_{1010}=I_3\overline{I_2}I_1\overline{I_0}$$

In hardware, inverters create the complemented forms and series/parallel transistor networks form the logical tests. Groups of related patterns can share intermediate terms, so the implementation need not build an entirely independent comparator for every instruction.

Eight Captured Bits Become a Hierarchy of Decisions OPR selects an operation family; OPA selects the member or operand INSTRUCTION REGISTER I7 I6 I5 I4 I3 I2 I1 I0 OPR · FAMILYOPA · SELECTION PRIMARY DECODE arithmetic · transfer · branch · memory recognize the broad instruction class SECONDARY DECODE register · condition · exact function refine the selected operation ONE QUALIFIED CONTROL WORD select source · select destination · choose operation · permit state change

## 2. Qualify Every Decode With the Correct Machine-Cycle Phase

A recognized opcode must not make every action happen at once. The multiplexed bus built in Step 3 supplies instruction bits during M1 and M2, while useful execution actions belong to later X phases. The instruction register holds the captured byte; timing logic then combines the stable decode with the current phase.

$$C_k(t)=D_{\mathrm{instruction}}\land P_k(t)\land Q_k$$

Here $D_{\mathrm{instruction}}$ says which instruction was recognized, $P_k(t)$ says that the correct phase is active, and $Q_k$ represents any required condition such as a carry flag or a selected register. Only the qualified control signal $C_k$ is allowed to change processor state. This prevents an instruction field from opening several data paths throughout the entire cycle.

The distinction is fundamental: decoding determines what the stored program requests; sequencing determines when each internal transfer may occur. Branch instructions add another decision by testing conditions, while two-byte instructions cause the control logic to retain the first-byte classification and treat the following byte as data or address information rather than a fresh independent opcode.

Decode Says What; the Phase Decoder Says When control is asserted only where instruction, time, and condition agree INSTRUCTION DECODE operation family + selectionstable after M1–M2 capture PHASE DECODE A · M · X timing windowsone scheduled moment STATE CONDITION carry · test · selected registerwhen required ANDqualify QUALIFIED CONTROL SIGNAL open one data pathselect one ALU functionwrite one destination the requested state change occurs only in its assigned phase

## 3. Reuse Silicon-Gate Manufacturing to Make Programmable Control Practical

The decoder's conceptual ingredients—AND, OR, inversion, storage, and gating—were not new in 1971. What made their concentration on the 4004 practical was the self-aligned silicon-gate MOS process this project established in its 1967 series. The same process foundation could form the instruction register, decoding networks, timing gates, and controlled internal paths together on one die. Step 4 therefore introduces a new organization of established devices, not a new transistor mechanism.

That organization is what separates a stored-program processor from a fixed-function calculator circuit. In fixed logic, the product's function is permanently expressed by one dedicated signal path. In the 4004, the decoder repeatedly maps changing instruction bits onto reusable hardware. The silicon stays the same while successive opcodes select different transfers and operations.

The MCS-4 manual describes a repertoire of 46 instructions, including arithmetic, data movement, conditional branching, subroutine control, and memory operations. The decoder supplies the mutually qualified control choices that distinguish them; it does not itself perform the arithmetic. Step 5 can now take those control signals into the four-bit arithmetic unit and show how binary addition is extended with decimal correction for the original calculator workload.

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