Microprocessor 1971 Store Program Separate Read Only Memory Chip

# Store the Program in a Separate Read-Only Memory Chip: Keep Instructions Stable Outside the Processor

## 1. Let the 4004 Select Instructions From a 4001 Program ROM

The Intel 4004 did not contain the program it executed. Its program counter generated an address, while a separate Intel 4001 chip stored 256 eight-bit instruction words in a mask-programmed read-only-memory array. The 4001 also included a four-bit input/output port, but its central role in instruction fetch was to convert the requested address into the next program byte.

Each 4001 stores

The twelve-bit program address is sent over the shared four-bit bus during A1, A2, and A3. The low and middle address groups select one of 256 word locations inside a 4001; the high group identifies the ROM chip. The selected 4001 then returns the eight-bit instruction as its upper OPR group during M1 and lower OPA group during M2. This is the address-and-data multiplexing from Step 3 put to a concrete purpose.

## 2. Encode the Program in the ROM Mask Instead of Rebuilding the CPU

In a mask-programmed ROM, the presence or absence of fabricated connections determines the stored bit pattern. The program is therefore fixed when the ROM's manufacturing mask is defined. Normal execution can select and read those bits repeatedly, but the 4004 cannot rewrite the 4001 array in the field.

This separation is the architectural breakthrough introduced in Step 1 made physical. The 4004 supplies a reusable fetch, decode, and execution engine; the 4001 supplies the application-specific instruction sequence. A calculator, controller, or another product can use the same processor design while pairing it with differently programmed ROM. What the system does moves out of the CPU's permanent wiring and into an ordered sequence of stored instruction words.

The separation also makes capacity modular. A twelve-bit program address spans 4,096 byte locations, and its high four-bit group can select among 4001 devices while the lower eight bits select one of 256 words within a chip:

The system can therefore grow its program store by adding ROM chips without widening the 4004's four-line data bus or redesigning its arithmetic core.

## 3. Distinguish Stable Program ROM From Writable, Refreshing DRAM

The 4001 and the 1968 one-transistor/one-capacitor DRAM cell both preserve information for later use, but they solve different storage problems. A mask ROM bit is embodied by a manufactured connection pattern. It is nonvolatile and requires no periodic refresh, but ordinary system operation cannot change it. A DRAM bit is represented by charge on a capacitor. It is writable at electronic speed, but leakage makes that state temporary, so sensing, restoration, and refresh are essential.

This is not a contest in which one memory is universally superior. Program instructions for a shipped calculator benefit from permanence; changing working quantities benefit from writability. The architecture assigns each kind of state to a storage technology whose physical behavior matches its role.

Step 6 completes the fetch path from program counter to external ROM and back to the instruction register. Step 7 will confront the timing consequence: because addresses and instructions share four pins, the processor and memory system require a coordinated multi-phase clock scheme to keep every transfer in order.