Microprocessor 1971 Classify Release Processor Architecture

# Classify and Release: The Architecture Every Later Chip Will Assume

## 1. Classify the 4004 as a CPU, Not as the Entire Computer

The Intel 4004 integrates the central processing functions—program counter, instruction register and decoder, registers, accumulator, arithmetic unit, branch control, timing, and memory control—onto one chip. It does not integrate the complete calculator or computer system. Program storage, working data storage, and expanded output remain in companion devices connected through the MCS-4 bus and control signals.

The released architecture is therefore a coordinated chip set:

This classification matters. Calling the 4004 a “computer on one chip” would erase the external program memory that supplies its behavior and the RAM that holds changing application data. Calling it merely another calculator circuit would miss the reusable instruction-processing engine whose final behavior is not fixed by the CPU layout.

## 2. Release a Fetch–Decode–Execute Architecture Whose Behavior Comes From Memory

The structure built across this series can now be stated as a closed loop:

1. The program counter identifies an instruction address.
2. The multiplexed bus carries that address to program ROM.
3. ROM returns an instruction byte in two four-bit groups.
4. The instruction register holds the byte while the decoder selects control signals.
5. Registers, arithmetic hardware, memory, or I/O perform the requested state change.
6. The program counter advances or a control-flow instruction replaces it, and the cycle begins again.

The decisive relationship is not any particular word width or opcode. The next machine state is selected by an instruction fetched from memory. The physical processor remains one manufactured circuit, while the instruction sequence determines which of its available state transitions occurs over time.

## 3. Separate the Enduring Abstraction From the 4004's Particular Constraints

Later microprocessors do not all preserve the 4004's four-bit word, 16-pin package, two-phase dynamic PMOS logic, eight-period cycle, external mask ROM, or distinct program and data interfaces. Some integrate memory controllers, caches, peripherals, multiple execution units, or entire systems on one die. Many execute several operations concurrently. Those are implementation choices, not the definition of the architectural inheritance.

What endures is the partition established here:

• A processor holds current state and implements a reusable set of operations.
• Program memory supplies encoded instructions rather than permanently wired behavior.
• A program counter and control flow determine which instruction comes next.
• A decoder converts instruction bits into timed internal control.
• Working memory and I/O connect computation to changing data and the outside world.
• A defined communication and timing protocol makes separately implemented blocks behave as one system.

The 4004's historical importance is therefore not that it was the fastest way to build every 1971 function. It demonstrated a commercially released general-purpose CPU on one silicon chip, surrounded by a coherent memory and I/O family, whose application followed from stored instructions. The calculator project produced an architecture that could outlive the calculator because the CPU did not permanently encode only that product.

With Step 10, the series is complete: it began by separating present inputs from remembered program state and ends with a processor-centered system in which addresses fetch instructions, instructions select reusable operations, and memory holds both enduring behavior and changing data. That is the architectural thread later microprocessors expand rather than replace.