MOSFET Scaling 1970s Confront Interconnect Scaling Mismatch

# MOSFET Scaling (1970s): Step 17 — Confronting the Interconnect Scaling Mismatch

Wires do not get faster the way transistors do. Dennard scaling predicts device delay improves proportionally with the scaling factor, but the metal and polysilicon interconnect wiring transistors together does not follow the same rule: wire resistance per unit length rises as cross-section shrinks, while wire capacitance per unit length falls more slowly, so RC interconnect delay does not shrink in step with device delay. Step 17 covers this emerging mismatch as it was first being recognized in the 1970s, well before it became a dominant concern in later scaling eras.

## 1. Why Wire Delay and Device Delay Scale Differently

Device switching delay in the Dennard framework scales down by the same factor k applied to geometry, roughly tracking L/v for a given velocity assumption. A wire's resistance scales as length over cross-sectional area, and if both the wire's width and thickness shrink by k while its length (set by chip layout, not by the scaling factor applied to an individual transistor) shrinks more slowly or not at all, wire resistance per unit length rises as roughly 1/k^2 even as the devices it connects get faster. The product of rising resistance and only slowly falling capacitance means RC wire delay can stay flat or even rise across a scaling generation that made every transistor faster.

## 2. Real Diagram: Device Delay vs. Interconnect Delay Across Scaling Generations

## 3. Why This Was a Second-Order Concern in the 1970s, Not Yet a First-Order One

At the chip sizes and clock rates of 1970s microprocessors and calculator chips, most critical paths were still dominated by device switching delay and logic depth rather than by long wire runs, so the interconnect mismatch identified in this step was recognized in the literature (including in follow-up work from Dennard's own group and others through the later 1970s) without yet forcing a redesign of interconnect materials or chip floorplanning practice. This step documents the mismatch at the point it was first becoming visible, which is also the point at which later scaling generations' much larger interconnect-driven design changes had their roots.

## 4. The Partial 1970s Response: Polysilicon as a Local Interconnect, Not a Long One

Recognizing that polysilicon (introduced for the self-aligned gate in step 6) has notably higher resistivity than aluminum, 1970s layout practice began explicitly restricting polysilicon to short, local interconnect runs — primarily gate electrodes and very short local routing — while reserving aluminum for longer signal and power routing, an early and direct response to the resistance-scaling problem identified in this step, well before more systematic interconnect scaling rules were developed in later decades.

## 5. Companion Diagram: Stage Sequence and Trend Summary

## Confronting the Interconnect Scaling Mismatch's Place in the Process Lineage

This is step 17 of 20 in the MOSFET Scaling (1970s) series, tracing planar NMOS scaling from early 1970s field pressure through the fixed-voltage-scaling break that opens the adjacent HMOS (1978) series.