MOSFET Scaling 1970s Confront Planar Nmos Scaling Pressure

# MOSFET Scaling (1970s): Step 1 — Confronting Planar NMOS Scaling Pressure

Why 1970s MOS logic could not simply keep using 1960s geometries. By the early 1970s, planar NMOS had replaced PMOS as the dominant logic technology because electrons move faster than holes in silicon, giving NMOS a speed advantage at a given geometry. But calculator and early microprocessor chips (Intel 4004, 8008) were pushing transistor counts into the thousands on a single die, and the straightforward response — shrink the mask geometry and keep every other parameter fixed — was starting to break the devices it produced. Step 1 frames the problem this 20-step series solves: scaling is not free, and doing it without a consistent rule set degrades yield, reliability, and noise margin faster than it buys density.

## 1. What 'Just Shrink It' Does to a 1960s-Style MOSFET

Early planar MOSFETs used channel lengths of 8-20 micrometers, gate oxides of 100-150 nanometers, and supply voltages fixed by TTL compatibility at 5 volts (often with separate higher bias rails). If a designer simply redrew the mask set at, say, 70% linear scale to gain density, three things happened at once: the electric field across the unchanged-thickness gate oxide rose because the same voltage now dropped across less material; the channel got short enough that the depletion regions from source and drain began to interact; and photolithographic alignment tolerances, which had not shrunk proportionally, started eating an unacceptable fraction of the smaller channel length as margin. None of these effects were new physics — they were consequences of changing one dimension without re-deriving the rest of the device.

## 2. Real Diagram: Unscaled Field Rise Under Naive Shrink

## 3. Why Voltage Could Not Simply Be Left at 5 V

Gate oxide breakdown strength in thermally grown SiO2 of this era was on the order of 8-10 megavolts per centimeter for routine production margins (intrinsic breakdown is higher, but manufacturable yield required headroom). A 150 nm oxide at 5 V sees roughly 0.33 MV/cm — comfortable. Shrink that oxide to 50 nm while keeping 5 V and the field triples to roughly 1 MV/cm at the gate, and local thinning or pinholes that would have been harmless at the thicker spec now have a meaningful chance of catastrophic breakdown during burn-in or field operation. This single number — the field across the gate dielectric — turns out to be the organizing constraint for everything that follows in this series, and it is why Robert Dennard's group at IBM spent the early 1970s looking for a scaling discipline rather than a one-off fix.

## 4. The Three Quantities Under Simultaneous Pressure

Three device parameters were moving at once and none of the three obvious 'fixes' (shrink only the channel, shrink only the oxide, or just raise doping) solved the problem alone: channel length L, oxide thickness t_ox, and supply voltage V_DD. Treating any one in isolation just moved the failure mode somewhere else — shrink L alone and short-channel leakage dominates; shrink t_ox alone without touching V_DD and you buy back speed at the price of oxide reliability; raise channel doping alone to suppress short-channel effects and threshold voltage and body effect get harder to control. Step 2 of this series takes up the formal answer Dennard's team published in 1974: scale all of the relevant quantities together by a single factor.

## 5. Companion Diagram: Stage Sequence and Trend Summary

## Confronting Planar NMOS Scaling Pressure's Place in the Process Lineage

This is step 1 of 20 in the MOSFET Scaling (1970s) series, tracing planar NMOS scaling from early 1970s field pressure through the fixed-voltage-scaling break that opens the adjacent HMOS (1978) series.