MOSFET Scaling 1970s Design Depletion Load Nmos Pair
# MOSFET Scaling (1970s): Step 11 — Designing the Depletion-Load NMOS Pair
How enhancement switch plus depletion load became the standard 1970s NMOS logic cell. With independent threshold control available (step 10), 1970s NMOS logic standardized on a two-transistor structure: an enhancement-mode device as the switching transistor and a depletion-mode device as its pull-up load, replacing earlier resistor-loaded or enhancement-loaded designs that were slower or less area-efficient. Step 11 covers why this specific pairing won out and what it demanded from the process.
## 1. Why Not a Resistor Load or an Enhancement Load?
A resistor load is simple but consumes chip area disproportionate to its function and gives a slow, non-ratioed pull-up. An enhancement-mode load transistor (gate tied to a separate higher supply, or to its own drain) works but its pull-up current falls as its own source rises toward V_DD minus its threshold, giving a relatively weak, voltage-dependent pull-up. A depletion-mode load — normally on, with its gate tied to its own source — supplies a comparatively constant current largely independent of the output node voltage, giving a sharper switching characteristic and faster rise time for a given device size.
## 2. Real Diagram: Enhancement Switch and Depletion Load Transfer Characteristic
## 3. The Aspect-Ratio Tradeoff This Pairing Introduced
Correct logic-level behavior requires the switching (enhancement) transistor to be considerably stronger than the load (depletion) transistor when the switch is on, which is achieved by sizing their width-to-length (aspect) ratios rather than relying on threshold alone — a wide, low-resistance switch against a narrow, higher-resistance load. Getting this ratio right, and keeping it consistent as both transistor types scale down together, becomes its own design discipline; getting it wrong either slows switching or burns static power through an imbalanced pair.
## 4. What This Cell Cost in Process Complexity
The depletion-load NMOS cell requires the fab to reliably produce two oppositely signed thresholds side by side on one chip, which is exactly the masked Vt-adjust implant capability introduced in step 10 — meaning the standardization of this logic cell and the standardization of implant-based threshold adjustment happened together, each enabling the other, rather than one simply following from the other.
## 5. Companion Diagram: Stage Sequence and Trend Summary
## Designing the Depletion-Load NMOS Pair's Place in the Process Lineage
This is step 11 of 20 in the MOSFET Scaling (1970s) series, tracing planar NMOS scaling from early 1970s field pressure through the fixed-voltage-scaling break that opens the adjacent HMOS (1978) series.