MOSFET Scaling 1970s Integrate Scaling Rules into Manufacturable Flow
# MOSFET Scaling (1970s): Step 18 — Integrating Scaling Rules Into a Manufacturable Flow
Turning nine separate fixes into one coherent, repeatable process. By the mid-to-late 1970s, this series has accumulated a long list of individually necessary process elements: generalized voltage/geometry scaling (steps 2-3), thin controlled gate oxide (step 4), self-aligned polysilicon gates (step 6), LOCOS isolation (step 7), shallow implanted junctions (step 8), implant-based Vt adjustment for dual-polarity devices (steps 9-11), heavier channel doping against rolloff (step 12), and channel-stop implants against isolation leakage (step 16). Step 18 covers the practical problem of sequencing all of these into one manufacturable flow without the fixes interfering with each other.
## 1. Ordering Constraints Between the Individual Fixes
Several of the process elements accumulated in this series have a required order relative to each other: LOCOS field oxidation (step 7) must happen before the self-aligned gate oxidation and polysilicon deposition (step 6) that defines the active-area gate, because LOCOS defines the active-area boundary the gate process works within; the channel-stop implant (step 16) is typically done through the same nitride mask used for LOCOS, meaning it has to be scheduled immediately adjacent to the LOCOS step rather than wherever would otherwise be convenient; and the Vt-adjust implant (step 10) must happen after gate oxide growth but before or through the polysilicon deposition, since it is specifically placed relative to the gate oxide interface. None of these orderings is arbitrary — each is forced by which structure needs to already exist before the next step can be positioned relative to it.
## 2. Real Diagram: Full Process Flow With Ordering Dependencies
## 3. Thermal Budget as the Resource Every Step Competes For
Every high-temperature step in the sequence — LOCOS field oxidation, gate oxidation, source/drain anneal — adds to the cumulative thermal budget the wafer has experienced, and dopant profiles placed earlier in the sequence (the Vt-adjust implant, the channel-stop implant) continue to diffuse slightly during every subsequent high-temperature step rather than staying frozen where they were placed. A flow that works fine for any one step in isolation can still fail if the cumulative thermal budget diffuses an early, carefully placed shallow implant deeper than its design intended by the time the whole sequence finishes — meaning the flow has to be validated as a whole, not step by step.
## 4. Why This Step Matters as Much as Any Individual Physics Fix
A process engineer in the late 1970s was not choosing between the fixes catalogued in this series — all of them were needed simultaneously once channel lengths dropped into the few-micrometer range — so the real engineering work increasingly shifted from inventing individual fixes to sequencing and thermal-budgeting the accumulated set of fixes into one wafer run that produced working, reliable, high-yield die. This integration discipline is what let the preceding seventeen steps' worth of individually necessary ideas become an actual manufacturing process rather than a list of papers.
## 5. Companion Diagram: Stage Sequence and Trend Summary
## Integrating Scaling Rules Into a Manufacturable Flow's Place in the Process Lineage
This is step 18 of 20 in the MOSFET Scaling (1970s) series, tracing planar NMOS scaling from early 1970s field pressure through the fixed-voltage-scaling break that opens the adjacent HMOS (1978) series.