MOSFET Scaling 1970s Push Channel Length Against Litho Limits

# MOSFET Scaling (1970s): Step 5 — Pushing Channel Length Against Lithography Limits

Mask alignment tolerance became the hard floor on channel length. Channel length is defined by the gap between source and drain diffusions, and in a 1970s non-self-aligned process that gap was set by two separate masking steps whose mutual alignment tolerance had to be added, not subtracted, from the design margin. Step 5 covers why this made channel length reduction harder than simply drawing a smaller box, and what it set up: the self-aligned polysilicon gate process covered in step 6.

## 1. The Alignment-Tolerance Floor on Non-Self-Aligned Channel Length

In a metal-gate or early non-self-aligned process, the gate electrode mask and the source/drain diffusion masks are separate layers, each positioned by a mask aligner with a finite registration tolerance (commonly several tenths of a micrometer in early-1970s contact aligners). To guarantee the gate still overlaps the full channel after worst-case misalignment, designers had to add overlap margin on both sides of the gate — margin that does not shrink just because the nominal channel length target shrinks. Past a certain point, alignment tolerance consumes a larger and larger fraction of the intended channel length, and shrinking the mask dimensions stops producing a proportionally shorter electrical channel.

## 2. Real Diagram: Alignment Margin Eating the Channel Budget

Fraction of Target Channel Length Consumed by Alignment Margin as nominal channel length shrinks, fixed alignment tolerance consumes a growing fraction of it nominal channel length target margin as fraction of channel length 20 µm 12 µm 8 µm 5 µm 3 µm 2 µm non-self-aligned processes hit a wall well before 2 µm — the structural motivation for step 6

## 3. Contact and Projection Aligner Improvements

Through the decade, aligner technology moved from contact printing (mask touching the wafer, prone to defects and limited registration) toward projection alignment, which improved registration accuracy and reduced defect-causing contact damage. This bought some headroom but did not eliminate the fundamental two-mask alignment problem — it just pushed the floor lower.

## 4. Why the Industry Needed a Structural Fix, Not Just a Better Aligner

The structural answer, covered next in step 6, was to stop using two independently aligned masks to define the channel at all. A self-aligned process defines the channel length as a direct geometric consequence of the gate electrode's own width, after which the diffusions are driven in using the gate itself as the mask edge — eliminating alignment tolerance as a channel-length budget item rather than merely shrinking it.

## 5. Companion Diagram: Stage Sequence and Trend Summary

MOSFET Scaling (1970s): Step 5 stage sequence and schematic outcome trend for this step The Alignment-Toler… 1 Real Diagram: Align… 2 Contact and Project… 3 Why the Industry Ne… 4 sequence progression outcome trend (schematic) companion diagram: stage sequence and schematic trend for this step

## Pushing Channel Length Against Lithography Limits's Place in the Process Lineage

This is step 5 of 20 in the MOSFET Scaling (1970s) series, tracing planar NMOS scaling from early 1970s field pressure through the fixed-voltage-scaling break that opens the adjacent HMOS (1978) series.

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