MRAM

MRAM stores a bit as the relative magnetic orientation of two ferromagnetic layers separated by a thin insulating barrier — parallel orientation reads as one resistance state, antiparallel reads as a noticeably higher one — and because that magnetic state holds its value with no power applied at all, MRAM combines DRAM-like speed and endurance with flash-like non-volatility, a combination neither of those two incumbent memory types can offer on its own.

Tunneling magnetoresistance, not a capacitor's stored charge or a floating gate's trapped electrons, is what MRAM actually reads, and that's the direct source of its non-volatility. A magnetic tunnel junction sandwiches an ultra-thin insulating barrier — typically magnesium oxide, just a few atomic layers thick — between two ferromagnetic layers, one with its magnetization permanently fixed and one free to switch; quantum mechanical tunneling lets current pass through that barrier at a rate that depends on whether the two layers' magnetic orientations align or oppose each other, and because a magnetic domain's orientation has no reason to decay once set (unlike a DRAM capacitor's charge, which leaks away in milliseconds and demands constant refresh), the stored bit survives indefinitely with the power completely off.

Spin-transfer torque is the mechanism that made MRAM commercially practical, replacing an earlier write approach that scaled badly as cells shrank. First-generation MRAM wrote bits using an external magnetic field generated by current flowing through nearby wires, which worked but required disturbingly high write currents and risked disturbing neighboring, unselected cells as density increased; spin-transfer torque instead passes a spin-polarized current directly through the MTJ stack itself, and that polarized current transfers angular momentum to the free layer's electrons, physically torquing its magnetization to flip when the current exceeds a threshold — a write mechanism that scales down with the cell itself rather than fighting against it, which is specifically why STT-MRAM, not field-switched MRAM, is what shipped in volume.

Writing still costs meaningfully more energy than reading, which is the central tradeoff that shapes where MRAM actually gets deployed. Flipping a stable magnetic domain against its own retention energy barrier inherently demands more current than simply sensing which state it's already in, so STT-MRAM write energy, while far better than flash's high-voltage programming, still runs higher than DRAM's read/write symmetry — this asymmetry is exactly why MRAM shows up first in embedded applications needing non-volatility with moderate write frequency, like automotive microcontrollers and industrial control systems, rather than displacing DRAM outright in main-memory roles where constant high-frequency writes would expose that energy gap.

Everspin and TSMC's embedded MRAM offerings represent two different commercial paths to the same underlying technology, aimed at different markets. Everspin builds standalone MRAM chips and has shipped STT-MRAM in volume for over a decade, targeting applications that need a drop-in non-volatile replacement for battery-backed SRAM or small flash parts; TSMC and other foundries instead offer embedded MRAM as a process module that can be integrated directly into a microcontroller or SoC's existing logic process, letting chip designers add non-volatile storage on-die without a separate memory chip — both paths rely on the same MTJ and STT physics, but target fundamentally different points in how a system actually uses non-volatile memory.

Read MRAM through a *magnetism-doesn't-decay* lens rather than a *faster-flash* lens: every other widely deployed memory technology stores its bit as a charge that either must be constantly refreshed (DRAM) or requires high-voltage programming to change (flash), while MRAM stores its bit as a magnetic orientation that costs nothing to maintain and only costs real energy at the moment of writing — a physical property, not a clever circuit trick, that is the entire reason MRAM can promise DRAM-class speed with flash-class persistence at once.