Multi Die Reticle Stitching
# Multi-Die Reticle Stitching
A lithography scanner's exposure field has a hard maximum size — roughly 26mm by 33mm for standard DUV and EUV scanners — and a reticle can only pattern that much area in a single exposure. The largest AI accelerator dies now routinely exceed what fits inside one field, pushed there deliberately to pack more compute onto a single piece of silicon. Reticle stitching is how those oversized dies get built anyway: pattern the die in multiple separate field exposures and align them so precisely at the seam that the stitched boundary behaves electrically like continuous silicon rather than two separate patterns glued together.
The stitch boundary has to carry real circuitry across it, which is what makes reticle stitching fundamentally harder than simply tiling two unrelated dies next to each other. A reticle-limited design splits its layout across field boundaries and relies on interconnect, power rails, and sometimes active devices to cross that boundary cleanly — the two exposures aren't independent circuits sitting side by side, they're one continuous design that happens to be patterned in separate passes. Overlay error at the stitch boundary isn't just a cosmetic misalignment; a few nanometers of registration error between the two field exposures can misconnect a wire crossing the seam or leave a via unlanded, turning a stitching tolerance problem directly into a yield-killing electrical defect right at the one location in the die that was always going to be hardest to pattern correctly.
Overlay control at the stitch seam gets a dedicated budget tighter than the rest of the die's own overlay spec, because the two field exposures have no shared reference the way two features inside one field do. Features patterned within a single exposure inherit whatever overlay error the scanner has for that one shot uniformly — relative registration between them stays tight even if the whole field is shifted slightly. Two separate field exposures stitched together have no such shared frame of reference; each exposure carries its own independent overlay error relative to the wafer, so the relative misalignment between them can be worse than the overlay spec either exposure individually meets. Fabs address this with dedicated stitch-specific alignment marks right at the seam and overlay metrology runs that measure stitch registration as its own tracked parameter, separate from the die's general overlay budget.
Reticle-stitched designs are a deliberate engineering tradeoff, chosen specifically when the compute density gain outweighs the yield risk the stitch seam introduces. A reticle-limited design can't simply shrink its way out of the problem — the whole point is maximizing compute on one die, which pushes toward the largest die size a process and packaging flow can support. Design teams at NVIDIA and other large-accelerator designers route the stitch boundary through the least timing-critical, lowest-density regions of the floorplan wherever the architecture allows, minimizing how much critical circuitry actually has to cross the seam, while accepting that the stitch region will carry somewhat elevated defect risk relative to the rest of the die in exchange for a die size no single reticle field could pattern any other way.
UCIe (568) solves the problem of connecting physically separate chiplets across a package boundary with a standard interface protocol. Reticle stitching solves a related but distinct problem one layer up in the hierarchy — building a single die larger than any one lithography field can pattern, with no package boundary or protocol layer at all, just continuous silicon that happens to be exposed in more than one pass.