multi-vdd design

**Multi-VDD design** is the chip architecture strategy of operating **different functional blocks at different supply voltages** — enabling fine-grained power-performance optimization where each block runs at the minimum voltage required for its specific performance target. **Why Multi-VDD?** - **Power-Performance Trade-off**: Higher voltage → faster transistors but more power. Lower voltage → slower but much less power. - **Quadratic Benefit**: $P_{dynamic} = \alpha \cdot C \cdot V_{DD}^2 \cdot f$. Even small voltage reductions yield significant power savings. - **Not All Blocks Are Equal**: A CPU core may need 1 GHz speed (requiring 0.9V), while a peripheral controller runs at 100 MHz (achievable at 0.65V). Running the peripheral at 0.9V wastes power. - **Multi-VDD** assigns each block its optimal voltage — maximizing overall energy efficiency. **Multi-VDD Architecture** - **Voltage Domains**: Each block (or group of blocks) at a specific voltage forms a voltage domain (voltage island). - **Level Shifters**: Required at every signal crossing between domains at different voltages: - **Low-to-High**: Signal from low-VDD domain driving into high-VDD domain. - **High-to-Low**: Signal from high-VDD domain driving into low-VDD domain. - **Power Supply Network**: Separate VDD rails for each voltage — multiple power grids on the chip. - **Voltage Regulators**: On-chip LDOs or external PMIC channels provide each voltage level. **Multi-VDD Techniques** - **Static Multi-VDD**: Fixed voltages assigned at design time. Each block always operates at its designated voltage. Simplest to implement. - **DVFS (Dynamic Voltage and Frequency Scaling)**: Voltage and frequency of a domain are adjusted at runtime based on workload. Maximum flexibility but requires voltage regulator with fast transient response. - **AVS (Adaptive Voltage Scaling)**: Voltage is automatically adjusted based on measured silicon performance — compensating for process and temperature variation. **Design Flow for Multi-VDD** 1. **Architecture**: Define voltage domains and assign voltages based on performance analysis. 2. **UPF/CPF**: Capture multi-VDD specification in power intent format. 3. **Synthesis**: Synthesize each domain with its target voltage library. Insert level shifters at domain crossings. 4. **Floorplanning**: Create physical regions for each voltage domain with separate power grids. 5. **P&R**: Route signals with level shifters at domain boundaries. Implement separate power grids. 6. **Timing**: Run MCMM analysis with each domain at its voltage across all PVT corners. 7. **Power Grid Analysis**: Verify IR drop and EM independently for each voltage domain. 8. **Verification**: Power-aware simulation ensures correct functionality across voltage transitions. **Multi-VDD Overhead** - **Level Shifters**: Each crossing adds area (~2–5× a buffer) and delay (~50–200 ps). Minimize domain crossings. - **Power Grid Complexity**: Multiple independent power grids increase routing complexity and area. - **Voltage Regulators**: Each domain needs a regulated supply — more regulators, more area, more complexity. - **Verification**: Must verify all combinations of voltage states across all domains. Multi-VDD is the **most effective architectural technique** for reducing SoC power consumption — it can reduce total power by **30–50%** by matching each block's voltage to its actual performance requirement.