N-Well
An n-well is a region of n-type silicon deliberately created within a p-type substrate to host devices that require an n-type local environment, most importantly the p-channel transistors of a CMOS circuit. It is one of the foundational structural features that make CMOS possible, because CMOS needs both n-channel and p-channel transistors on the same chip, and those two transistor types require oppositely-doped local regions to be built in. The n-well is the tub of n-type material, formed in a p-type wafer, inside which the p-channel transistors live, electrically distinct from the surrounding substrate where the n-channel transistors are built.
The reason an n-well is needed comes directly from how the two CMOS transistor types are constructed: each needs a body region of the opposite doping to its channel. An n-channel transistor is built in p-type material, and a p-channel transistor is built in n-type material. If the wafer substrate is p-type, the n-channel transistors can be built directly in it, but the p-channel transistors need a pocket of n-type material to sit in. The n-well provides that pocket, allowing both polarities of transistor to coexist on one p-type wafer, which is exactly what CMOS requires. Without the well, only one transistor type could be built in the substrate.
An n-well is formed by introducing n-type dopants into selected regions of the p-type wafer and driving them in to create a counter-doped tub. Dopant atoms that make silicon n-type are introduced into the chosen areas, typically by implantation, and then diffused to the required depth, overwhelming the background p-type doping in those regions and converting them to n-type. The result is a well-defined region of n-type silicon embedded in the p-type substrate, with a junction at its boundary that helps keep it electrically separate. Inside this tub, p-channel transistors are then fabricated as if they were in an n-type wafer.
The n-well is part of a broader family of well strategies, and the choice among them reflects trade-offs in how independently the two transistor types can be optimized. A process may use an n-well in a p-substrate, a p-well in an n-substrate, or a twin-well approach that forms both n-wells and p-wells so that each transistor type sits in a custom-doped region tailored to its needs. The twin-well approach gives designers more freedom to optimize both transistor polarities independently, at some added process complexity. The n-well is thus one option within a design space whose common purpose is providing each transistor type the local doping environment it requires.
The n-well also plays a role in managing latch-up, the parasitic conduction hazard that CMOS structures are prone to, because well design affects the parasitic devices between the transistors. The adjacent n-type and p-type regions in a CMOS layout form parasitic bipolar structures that, under certain conditions, can trigger a self-sustaining low-resistance path from supply to ground. Careful design of the wells and their contacts helps suppress this latch-up, so the n-well is not only about hosting transistors but also about controlling the parasitic interactions inherent in placing complementary devices close together. This makes well engineering a meaningful part of CMOS reliability.
Read the n-well as the n-type tub that lets p-channel transistors live on a p-type wafer: the counter-doped pocket that makes complementary CMOS possible by giving each transistor polarity the body it needs, one of a family of well strategies whose design also governs the latch-up hazard of placing opposite devices side by side.