3D NAND Reference Diagram

# Inside the 3D NAND Cell — and Why Layer Count Replaced Lithographic Pitch

a macaroni-channel charge-trap cell, and the scaling curve it made possible

Lithographic pitch stopped scaling the planar cell around the 2010s; stacking more tungsten/oxide pairs — and later, more decks — kept density climbing instead.

CMOS-Under-Array (CuA/Xtacking) frees the die area periphery logic used to occupy, by bonding it face-to-face beneath the array — stacking that works alongside deck-stacking, not against it.

For the invention history of charge-trap storage, see eprom_eeprom_history · for a denser single-article treatment, see nand_complete_art / nand_400_layer_art