3D NAND
# Confront the Tunnel-Oxide Atomic-Scale Limit
## 2. 2. Confront the Tunnel Oxide Atomic Scale Limit
A second wall sat beside the first, and it was arguably harder to argue around: the tunnel oxide itself. Flash memory, the floating-gate storage concept underneath both NOR and NAND flash, was invented by Fujio Masuoka at Toshiba in the early 1980s, with the NAND architecture specifically following later in the decade as a denser, serial-string alternative to NOR flash's more random-access-friendly layout; that invention history, and the earlier EEPROM/EPROM floating-gate work it built on, is told in full elsewhere on this site in the `eprom_eeprom_history` series and is only named here for context, not retold. What matters for this series is what happened to that floating-gate cell as planar scaling continued for another twenty-five years after Masuoka's invention: the tunnel oxide, the thin insulating layer that charge must tunnel through to get on and off the floating gate, had to get thinner at almost every node to keep the cell's electrical characteristics in range. By the time planar NAND reached its smallest commercial nodes, that oxide was only a handful of atomic layers thick. An oxide that thin leaks charge more readily, reduces the safety margin against two bits being mistaken for each other, and offers less margin for the wear a cell accumulates over its program/erase lifetime. There was no path to a meaningfully thinner tunnel oxide left to take — the industry was no longer scaling a transistor, it was approaching the physical limit of how few atoms can still act as a reliable insulating film.