What Is NAND Device Architecture

A NAND device architecture is the comprehensive physical, electrical, and structural organization of NAND flash memory—encompassing both classic planar (2D) floating-gate arrays and modern vertical (3D) charge-trap superlattices, memory string organizations, high-voltage peripheral drivers, page buffers, and high-speed multi-gigabit PHY interfaces. Invented by Dr. Fujio Masuoka at Toshiba in 1989, the foundational principle of a NAND device architecture is the series-connected memory string: unlike NOR flash—where every cell connects directly to a metal bitline in parallel, demanding a large contact area—NAND strings connect 32 to over 128 cells end-to-end between a single bitline contact and a common source line. This series architecture reduces cell footprint by $>60\%$ compared to NOR, providing the highest storage density and lowest cost-per-gigabyte in the semiconductor industry. Modern NAND architectures span the continuum from sub-20nm planar floating-gate cells (limited by capacitive cell-to-cell coupling and few-electron leakage) to multi-tier 3D charge-trap strings exceeding 200 to 300 vertical layers with CMOS Under Array (CuA) integration. At a high level, the architectural anatomy of a NAND device and its core read, program, and block-erase cycle looks like this:

A few principles are essential for understanding how NAND device architectures are constructed, how series-string topology balances density against latency, and why architectural evolution transitioned from planar floating gates to vertical charge traps:

Device structural hierarchy: cell, string, page, block, and plane. A NAND device architecture is organized into five nested physical and logical domains:
1. *The Unit Memory Cell (Floating Gate vs. Charge Trap):*
- *Planar Floating Gate (FG):* A polysilicon conductive storage island isolated between a thin tunneling oxide ($7\text{–}9\text{ nm}$) and an inter-poly dielectric (IPD, typically $SiO_2/Si_3N_4/SiO_2$ ONO). Below the $15\text{ nm}$ node, parasitic capacitive coupling between adjacent floating gates ($C_{\text{inter-cell}}$) and few-electron leakage through thin tunneling oxides halted planar scaling.
- *Charge Trap Flash (CTF):* Employs an insulating silicon nitride ($Si_3N_4$) layer with localized deep-level traps. Because trapped electrons cannot move freely, a localized defect in the tunneling dielectric does not drain the entire stored charge, dramatically enhancing retention and endurance.
2. *The Series NAND String:*
- Typically comprises 32, 64, or 128 cells connected in series, flanked by a Drain Select Gate (SGD) connected to the metal bitline and a Source Select Gate (SGS) connected to the common source line (CSL).
- In a series string, individual cells do not have bitline contact vias; instead, the source of one cell forms the drain of the adjacent cell directly within continuous silicon or vertical channel macaroni.
3. *Pages and Wordlines (Unit of Read/Program):*
- All cells sharing the same control wordline across thousands of bitlines form a *page* (typically $4\text{ KB to }16\text{ KB}$ plus spare ECC bytes). Read and program operations are executed strictly on a whole-page basis.
4. *Memory Blocks (Unit of Erase):*
- A *block* consists of all pages sharing the same set of NAND strings (typically 128 to 512 pages, totaling $4\text{ MB to }32\text{ MB}$). Because the entire p-well substrate or source plane is shared across the string group, erasing can only be performed at the block level by driving a high bulk erase potential ($V_{\text{ERA}} \approx 20\text{ V}$).
5. *Planes and High-Speed Periphery:*
- Modern NAND dies are divided into 2, 4, or 6 independent *planes*, each equipped with dedicated page buffers and row decoders. Multi-plane operations allow concurrent read, write, or erase execution across planes, multiplying host bus throughput.

Asymmetric read, write, and erase physics and reliability trade-offs. The physical nature of NAND device architectures creates fundamental operational asymmetries that dictate modern solid-state drive (SSD) controller algorithms:
- *Program Disturb and Channel Self-Boosting:* During page programming, applying $V_{\text{PGM}} \approx 20\text{ V}$ to a selected wordline risks inadvertently programming unselected cells on the same wordline that belong to other bitlines. To inhibit tunneling in unselected cells, the memory architecture floats unselected bitline strings by applying $V_{\text{DD}}$ to their Drain Select Gates ($SGD$), turning them off. When the unselected wordlines ramp to $V_{\text{PASS}} \approx 9\text{ V}$, capacitive cross-coupling between the wordlines and the floating channel lifts the channel potential to $V_{\text{channel}} \approx 7\text{–}8\text{ V}$ (self-boosting), dropping the effective tunneling oxide voltage below the injection threshold.
- *Write Amplification and Asymmetric Block Erasing:* Unlike DRAM or SRAM—where individual bits or bytes can be overwritten in place—NAND flash can only program cells in the '1' to '0' direction. Reverting a '0' back to a '1' requires an erase operation, which cannot be executed on a page basis because all strings in a block share the common substrate well. Consequently, modifying a single $4\text{ KB}$ page requires the SSD controller to perform out-of-place writes, track invalid pages, and periodically execute *garbage collection* (reading valid pages out, erasing the entire $16\text{ MB}$ block, and rewriting valid pages), causing Write Amplification ($WA > 1.0$).
- *Endurance Degradation and Oxide Trap Generation:* Every Fowler-Nordheim write and erase cycle forces high-energy electrons through the thin tunneling dielectric. Over time, energetic carriers create silicon-oxygen bond ruptures ($E'$ centers) and interface traps ($D_{\text{it}}$). These trapped charges cause threshold voltage drift, widen $V_{\text{th}}$ distributions, and introduce stress-induced leakage current (SILC), eventually reducing memory retention and defining the finite cycle limit ($10^4\text{ to }10^5$ cycles for SLC; $10^3\text{ to }3\times 10^3$ for TLC; $500\text{ to }10^3$ for QLC).

Read a NAND device architecture through a *series-density-and-quantum-tunneling* lens: an ingeniously optimized storage topology where series-connected strings eliminate redundant contact overhead, trading byte-level writability for unprecedented terabit density and non-volatile endurance that underpins the entire modern cloud data ecosystem.