Nanosheet-Stack-Count
Nanosheet stack count is the number of vertically stacked semiconductor channel sheets in one gate-all-around transistor stack. The sheets provide parallel paths between source and drain, usually controlled by one connected gate electrode. Adding sheets can increase channel perimeter within a similar lateral footprint, but also changes capacitance, vertical dimensions and manufacturing demands. It is a device-architecture parameter to evaluate alongside sheet width, thickness, spacing and contact design, rather than a standalone measure of process quality.
Count the surviving channels in one stack. A three-sheet stack contains three channel bodies at different heights, each surrounded by gate dielectric and gate metal in the gate region. They are parallel channels of one transistor, rather than three independently controlled transistors. Sacrificial layers removed during fabrication are excluded. A CFET instead places complementary transistor tiers above one another; each tier can contain its own nanosheet stack. NAND layer count, metal-layer count and lateral duplication of transistor stacks describe other structures.
Sheet count and sheet width both contribute to geometric channel perimeter. For identical rectangular sheets, a simple estimate is W_eff,geom ≈ 2 × N × (W + T), where N is count, W is sheet width and T is thickness. As an illustrative calculation, W = 40nm and T = 5nm give 270nm of perimeter for three sheets and 360nm for four: a one-third increase. This is geometry accounting, not a measured current or frequency result. Rounded corners, confinement and different crystal-face mobilities complicate electrical interpretation.
More current comes with more charge to switch. Extra parallel channels can raise drive current, while their additional gated surface also increases gate capacitance. Contacts and source/drain regions introduce resistance shared by the channels, so delivered current need not scale linearly with count. The rough circuit relation delay ≈ C_load × V / I_drive explains why the outcome depends on loading: both the available current and the capacitance can change. A fixed external load and a chain of similarly enlarged devices therefore need separate evaluation.
The process must form and access every channel. One established silicon nanosheet route starts with alternating silicon and sacrificial silicon-germanium layers. Selective removal releases the channels; dielectric and gate materials must then reach the spaces around them. IBM’s research describes channel-release selectivity and work-function integration as important parts of the technology. More layers make uniform formation, release and access throughout the taller structure significant integration questions. The process drawing below omits source/drain supports and inner spacers to keep the retained channel count visible.
Stack height is a separate constraint from cell height. With uniform sheet thickness T and clear gap G, the channel-stack span is approximately H = N × T + (N − 1) × G. This excludes the upper and lower gate enclosure, isolation, contacts and other integration allowances. Keeping N fixed while reducing G saves vertical space, but leaves less room for gate dielectric and work-function materials. Standard-cell height describes a layout dimension in the wafer plane. Increasing vertical sheet count does not by itself establish how that lateral cell dimension changes.
The useful choice belongs to a qualified process and circuit. A foundry defines which device geometries and options its models, fabrication flow and libraries support. Designers cannot assume that adding one sheet is an available per-transistor layout switch. Width tuning, parallel devices and library drive-strength choices are separate options whose availability also depends on the platform. Compare stack counts using matched gate length, bias, leakage target, contact design, footprint and load, then check routed timing, energy and variation. A microscopy image or schematic alone cannot supply those circuit results.
Sources and further reading. [IBM’s stacked-nanosheet GAA demonstration, VLSI 2017](https://research.ibm.com/publications/stacked-nanosheet-gate-all-around-transistor-to-enable-scaling-beyond-finfet); [IBM on sheet spacing, channel release and multiple threshold voltages](https://research.ibm.com/blog/nanosheet-technology-ai-5g); [Samsung’s MBCFET channel-width and stacking explanation](https://semiconductor.samsung.com/news-events/tech-blog/samsung-opens-the-gate-to-transistor-performance-power-and-area-improvements-with-mbcfet/); [Research on four-layer silicon nanosheet device integration](https://doi.org/10.3390/nano11030646).
Read nanosheet stack count as one physical design variable: connect the number of channels to their geometry, current, capacitance, process margin and measured circuit behavior.