network on chip
**Network-on-Chip (NoC)** — a packet-switched communication fabric that replaces traditional shared buses for connecting many IP blocks in large SoCs, providing scalable bandwidth and reducing wiring congestion.
**Why NoC?**
- Shared bus: One master talks at a time. Doesn't scale beyond ~10 agents
- Crossbar: Full connectivity but O(N²) wires. Doesn't scale beyond ~20 ports
- NoC: Packet-based network with routers. Scales to 100+ endpoints
**Architecture**
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- Each IP block connects to a Network Interface (NI)
- Routers forward packets based on destination address
- Common topologies: Mesh (2D grid), Ring, Tree, Torus
**Key Features**
- **Quality of Service (QoS)**: Priority-based routing (CPU traffic > background DMA)
- **Virtual channels**: Multiple logical channels per physical link (prevent deadlock)
- **Flow control**: Credit-based or wormhole routing
- **Bandwidth**: 100+ GB/s aggregate bandwidth for large SoCs
**Commercial Solutions**
- Arteris FlexNoC (most widely licensed NoC IP)
- Synopsys NoC
- ARM CMN (Coherent Mesh Network) — used in Neoverse server processors
**NoC** is the circulatory system of modern SoCs — as chips grow to billions of transistors with dozens of IP blocks, scalable interconnect becomes critical.