network on chip design

**Network-on-Chip (NoC) Architecture** is the **structured communication fabric that replaces ad-hoc wire-based interconnects with a packet-switched or circuit-switched network of routers and links — providing scalable, modular, and bandwidth-guaranteed communication between IP blocks (CPU cores, GPU clusters, memory controllers, accelerators) in large SoCs where point-to-point wiring becomes impractical at dozens to hundreds of on-chip endpoints**. **Why NoC Over Bus or Crossbar** Traditional shared buses bottleneck at 4-8 masters. Crossbar switches provide full connectivity but scale as O(N²) in area and wires. NoC scales gracefully: adding an IP block requires adding one router and local links, while the rest of the network is unchanged. NoC also enables structured design methodology — the communication architecture is designed once and reused across products. **NoC Components** - **Router**: Receives packets, examines the destination address, and forwards through the appropriate output port. Typical router: 5 ports (4 cardinal directions + local), 2-4 cycle latency, 128-512 bit flits (flow control units). Pipeline stages: route computation, virtual channel allocation, switch allocation, switch traversal. - **Link**: Physical wires connecting adjacent routers. Width: 128-512 bits. At 5nm and 1 GHz, links consume 0.1-0.5 pJ/bit/mm. - **Network Interface (NI)**: Converts between the IP block's native protocol (AXI, CHI, TileLink) and the NoC's packet format. Handles packetization, de-packetization, and protocol translation. **Topology Options** - **2D Mesh**: Most common. Routers arranged in a grid, each connected to 4 neighbors. Diameter = 2(√N-1) hops for N routers. Simple layout, regular structure, easy physical design. - **Ring**: Low cost (2 links per router). High diameter (N/2 hops for N routers). Used for small-scale NoCs (4-8 nodes) or as a secondary interconnect. - **Hierarchical Mesh**: Cluster-level local rings or meshes connected by a global mesh. Exploits traffic locality — most communication stays within a cluster. **Flow Control and Quality of Service** - **Virtual Channels (VCs)**: Multiple logical channels share one physical link. VCs prevent deadlock (by providing escape paths) and enable QoS (priority traffic uses dedicated VCs). - **Credit-Based Flow Control**: Downstream router sends credits to upstream when buffer space frees. Prevents buffer overflow without wasting bandwidth. - **QoS**: Real-time traffic (display, audio) gets guaranteed bandwidth and latency through dedicated VCs or bandwidth reservation. Best-effort traffic (CPU-memory) fills remaining bandwidth. **Power Optimization** NoC can consume 10-30% of total SoC power. Clock gating idle routers, power gating unused links, voltage scaling of the mesh domain, and narrow-link modes during low-bandwidth periods reduce NoC power proportional to actual traffic load. NoC Architecture is **the on-chip communication infrastructure that enables the many-core era** — providing the scalable, structured, and quality-of-service-aware interconnect fabric without which modern SoCs containing billions of transistors organized into hundreds of functional blocks could not function coherently.