nickel silicide NiSi
**Nickel and Nickel-Platinum Silicide (NiSi, Ni(Pt)Si)** are the **self-aligned silicide (salicide) materials formed on source/drain and gate contacts to reduce contact resistance**, replacing earlier TiSi₂ and CoSi₂ at advanced nodes due to lower formation temperature, lower silicon consumption, and better scaling to narrow junctions — though facing increasing challenges at FinFET and GAA dimensions.
**Silicide Purpose**: The interface between metal interconnects and doped silicon has inherently high resistance. Silicide provides a low-resistivity conducting layer (~15 μΩ·cm for NiSi) that bridges this interface, enabling ohmic contact. The salicide (self-aligned silicide) process forms silicide only where metal contacts bare silicon, using gate spacers and STI as natural masks.
**Salicide Process Flow (NiSi)**:
| Step | Process | Key Parameters |
|------|---------|---------------|
| 1. Pre-clean | HF dip + sputter clean | Remove native oxide |
| 2. Metal deposition | PVD Ni or Ni(Pt) (5-10nm) | Thickness controls silicide depth |
| 3. First anneal (RTP1) | 250-350°C, 30-60 sec | Form Ni₂Si (metal-rich phase) |
| 4. Selective metal strip | Wet etch (H₂SO₄:H₂O₂ or HNO₃:HCl) | Remove unreacted Ni from spacers/STI |
| 5. Second anneal (RTP2) | 400-550°C, 30 sec | Convert Ni₂Si → NiSi (low resistance) |
**Why NiSi Replaced CoSi₂**: At the 65nm node and below, CoSi₂ had critical limitations: **narrow line effect** (resistance increases sharply for lines <40nm wide due to nucleation difficulties), high formation temperature (700-800°C, incompatible with SiGe S/D), and high silicon consumption (required ~3.6× the Co thickness in Si). NiSi solves all three: no narrow-line effect, lower formation temperature (400-550°C), and lower Si consumption (~1.8× Ni thickness).
**Ni(Pt)Si — Platinum Stabilization**: Pure NiSi is metastable — it transforms to high-resistivity NiSi₂ at temperatures above ~700°C (occurring during subsequent BEOL processing). Adding 5-15 atomic% Pt: raises the NiSi₂ transformation temperature by 50-100°C, improves morphological stability (reduces agglomeration), and provides better thermal stability of the silicide/silicon interface. Ni(Pt)Si has been the standard contact silicide since the 45nm node.
**Silicide at FinFET and GAA Nodes**: Challenges multiply: the silicide must form conformally on the 3D fin or nanosheet surfaces; the available silicon volume is very small (thin fins, thin sheets), limiting maximum silicide thickness; and the S/D epi material is SiGe or SiC:P rather than pure silicon, requiring modified process conditions. Some processes skip traditional silicide entirely, using direct metal deposition (Ti + TiN liner) to make contact to the S/D epi.
**Contact Resistance Engineering**: At sub-7nm nodes, the contact resistance (Rc) between the silicide and the doped S/D becomes a dominant component of total parasitic resistance. Rc depends on the Schottky barrier height (ΦB) and doping at the contact: Rc ∝ exp(ΦB·√(m*/N_D)). Solutions: higher doping (approaching solid solubility >2×10²¹ cm⁻³), interface dipole layers (TiO₂, La₂O₃ to reduce ΦB), and novel contact metallurgies.
**Nickel silicide technology has been the workhorse contact material for over a decade of CMOS scaling — yet the relentless shrinkage of contact dimensions and the shift to 3D transistor architectures are pushing even this mature technology toward its limits, driving innovation in contact engineering that is as intense as the transistor channel innovation it serves.**