contact silicide formation

**Contact and Silicide Formation Process** — Essential metallization steps that create low-resistance electrical connections between transistor terminals and the back-end-of-line interconnect system through controlled metal-silicon reactions. **Self-Aligned Silicide (Salicide) Process** — The salicide process deposits a thin metal film (typically 8–15nm) over the entire wafer surface, followed by thermal annealing to form metal silicide selectively on exposed silicon and polysilicon regions. Unreacted metal on dielectric surfaces is removed by selective wet etching, leaving silicide only on source/drain and gate contacts. Nickel silicide (NiSi) has replaced cobalt and titanium silicides at advanced nodes due to its lower formation temperature (300–450°C), reduced silicon consumption, and lower sheet resistance on narrow lines. NiPt alloys with 5–10% platinum improve NiSi thermal stability by suppressing the high-resistivity NiSi2 phase transformation. **Contact Resistance Engineering** — As device dimensions shrink, contact resistance increasingly dominates total parasitic resistance, accounting for over 50% of source/drain series resistance at sub-14nm nodes. Interface resistance at the silicide-silicon junction follows the relationship Rc ∝ exp(ΦB/√N), where ΦB is the Schottky barrier height and N is the doping concentration. Dual silicide approaches using different metals for NMOS and PMOS optimize barrier heights for each carrier type. Ti-based liners in contact trenches form TiSi2 interfaces with barrier heights below 0.3eV when combined with heavy doping exceeding 2×10²¹ cm⁻³. **Contact Module Integration** — Middle-of-line (MOL) contact formation involves dielectric deposition, contact hole patterning and etching, barrier/liner deposition, and tungsten or cobalt plug fill. Contact etch must stop precisely on the thin silicide layer without punch-through into the underlying junction — etch selectivity between the PMD oxide and silicide exceeding 20:1 is required. At advanced nodes, cobalt and ruthenium contact fills replace tungsten to eliminate the resistive TiN barrier layer and reduce effective contact resistivity in aggressively scaled contact dimensions below 20nm. **Silicide Thermal Stability and Defects** — Silicide agglomeration during subsequent thermal processing creates voids and increases sheet resistance, particularly on narrow active areas where grain boundary diffusion accelerates morphological degradation. Millisecond laser annealing and flash annealing techniques limit the thermal budget seen by the silicide while still activating source/drain dopants. Silicide-induced junction leakage from metal pipe defects penetrating into the depletion region requires careful optimization of metal thickness, anneal temperature, and pre-clean surface preparation. **Contact and silicide process optimization is critical for maintaining parasitic resistance within acceptable limits, directly impacting transistor drive current and circuit speed as contact dimensions continue to scale with each technology generation.**