silicide formation
**Silicide Formation** — creating a metal-silicon compound on the surface of source, drain, and gate to dramatically reduce contact resistance, a critical step for transistor performance.
**Why Silicide?**
- Doped silicon resistivity: ~500–1000 μΩ·cm
- Silicide (NiSi) resistivity: ~15–20 μΩ·cm (50x lower)
- Without silicide: Source/drain sheet resistance would dominate, killing transistor speed
**Self-Aligned Silicide (Salicide) Process**
1. Deposit metal uniformly (Ni, Co, or Ti)
2. First anneal: Metal reacts with exposed Si to form metal-silicide (on source, drain, gate)
3. Metal on oxide/nitride spacers does NOT react (remains unreacted)
4. Selective wet etch: Remove unreacted metal from spacers. Silicide remains only where needed
5. Second anneal: Convert to low-resistivity phase
**Silicide Evolution**
| Generation | Material | Resistivity | Nodes |
|---|---|---|---|
| 1990s | TiSi₂ | 15 μΩ·cm | 0.35–0.18 μm |
| 2000s | CoSi₂ | 18 μΩ·cm | 130–65 nm |
| 2010s+ | NiSi | 15 μΩ·cm | 45 nm – current |
| Future | Ti silicide (revisited) | ~15 μΩ·cm | GAA era |
**Challenges at Advanced Nodes**
- Smaller contact area → higher total resistance even with low-resistivity silicide
- Agglomeration: Thin silicide films become unstable at high temperatures
**Silicide** is invisible to the circuit designer but essential — it's what makes the connection between the transistor and the metal wiring efficient.