nickel silicide formation

**Silicide Formation NiSi TiSi** is a **metallurgical process reacting transition metals with silicon forming low-resistance compounds that provide superior electrical contact to silicon transistor junctions — essential for reducing parasitic series resistance in ultrascaled devices**. **Salicide Technology and Process** Salicide (self-aligned silicide) technology employs metal deposition followed by thermal annealing creating metal-silicon compound with lower resistivity than either constituent material. Nickel silicide (NiSi) dominates modern CMOS: nickel deposited via sputtering (30-100 nm thickness) onto silicon surfaces (source/drain regions, gate); rapid thermal annealing (600-800°C) initiates solid-state reaction forming NiSi. Self-alignment achieved through fundamental process mechanics: nickel reacts only with exposed silicon surfaces; dielectric-covered regions remain metal (metal agglomerates into balls if left), easily removed via selective etch. Result: silicided regions perfectly aligned to lithographic patterns with no overlay tolerance issues. **Nickel Silicide Formation Phases** Ni-Si system exhibits multiple intermetallic phases: NiSi (monoclinic, low resistivity 10-20 μΩ-cm), Ni₂Si (orthorhombic, higher resistivity ~35-40 μΩ-cm), and NiSi₂ (cubic, very high resistivity). Thermal annealing temperature determines phase: 400-500°C forms Ni₂Si (kinetically favored); 550-650°C converts to NiSi (thermodynamically favored); exceeding 750°C potentially forms NiSi₂. Process strategy: low-temperature anneal creating Ni₂Si, then higher temperature conversion to NiSi during subsequent processing steps. Controlling anneal temperature within ±10°C critical for phase control. **Resistivity and Contact Characteristics** - **NiSi Resistivity**: Bulk 10-15 μΩ-cm, comparable to copper (1.7 μΩ-cm) but superior to tungsten (5.5 μΪ-cm) among refractory materials - **Contact Resistance**: Specific contact resistivity (ρc) typically 10⁻⁷-10⁻⁸ Ω-cm² on heavily doped silicon; thin silicide layer (10-30 nm) achieves total contact resistance <10 Ω - **Thermal Coefficient**: NiSi resistivity increases ~0.3%/°C; good stability across wide temperature range (-40°C to +150°C) with <15% variation - **Grain Structure**: Polycrystalline NiSi exhibits columnar grains aligned with underlying silicon; grain boundaries contribute minimal scattering for <100 nm film thickness **Titanium Silicide Alternative** - **TiSi₂ Formation**: Titanium silicide (TiSi₂) forms at lower temperature (700-800°C) compared to nickel; higher resistivity (15-25 μΩ-cm) than NiSi but adequate for many applications - **Phase Purity**: TiSi₂ exhibits less complex phase diagram than Ni-Si; simpler processing with reduced phase control sensitivity - **Barrier Properties**: TiSi₂ provides superior barrier against dopant diffusion; beneficial for advanced devices requiring minimal dopant movement **Process Integration Steps** - **Nickel Deposition**: Sputtering or evaporation deposits uniform 30-100 nm nickel; thickness determines final silicide thickness (silicon consumes stoichiometric amount during reaction) - **Silicidation Anneal**: Rapid thermal annealing (RTA) at 550-700°C, duration 10-60 seconds initiates reaction forming NiSi - **Unreacted Metal Removal**: Wet etch (aqua regia: HNO₃ + HCl, or HF-based solution) selectively removes unreacted nickel leaving only silicided regions - **Anneal Optimization**: Optional second anneal at 800-900°C (lower temperature than initial) stabilizes NiSi phase, reduces resistivity 5-10% through defect annealing **Advanced Silicide and Emerging Materials** Recent development: cobalt silicide (CoSi₂) showing promise through improved thermal stability and lower agglomeration compared to NiSi at advanced nodes. Platinum-based silicides (PtSi) used in specialized applications (Schottky barriers) but cost-prohibitive for mainstream CMOS. Research-stage materials: fully silicided (FUSI) gates employ metallic silicide replacing polysilicon gate (gate-first approaches) or replacing polysilicon entirely (metal gates) enabling lower work-function adjustment without polysilicon depletion effects. **Scaling Challenges and Future Direction** Advanced nodes (10 nm and below) face silicide scaling challenges: as junction depth reduces below 20 nm, silicide thickness becomes comparable to depletion width; silicide-junction interface interaction affects threshold voltage. Elevated temperature silicidation enables phase control but risks dopant diffusion broadening junctions. Gate-first metal replacement (TiN, TaN stacks replacing polysilicon) eliminates gate silicide complications; tradeoff: additional thermal budget impact on junction profiles. **Closing Summary** Silicide technology represents **a fundamental metallurgical innovation leveraging metal-silicon reaction thermodynamics to achieve low-resistance contacts essential for scaling — through precise thermal control of phase formation and unreacted material removal enabling seamless integration into CMOS process flows without introducing overlay complexity**.