on chip network noc

**Network-on-Chip (NoC)** is the **scalable on-chip communication infrastructure that replaces traditional bus and crossbar interconnects in complex SoCs — using packet-switched routing through a network of on-chip routers connected in mesh, ring, or tree topologies to provide high-bandwidth, low-latency communication between dozens to hundreds of IP blocks while maintaining manageable wiring complexity and design modularity**. **Why NoC Replaced Buses** Traditional shared buses (AMBA AHB) don't scale beyond ~10 masters — arbitration latency grows linearly with masters, and the shared medium creates a bandwidth bottleneck. Crossbars (AMBA AXI with NIC-400) scale better but wiring grows as O(N²), becoming impractical beyond ~20 ports. NoC provides O(N) wiring growth with O(N) aggregate bandwidth, scaling to 100+ endpoints. **NoC Architecture** - **Network Interface (NI)**: Adapts IP block protocols (AXI, CHI) to NoC packet format. Handles packetization, flow control, and protocol conversion. Each IP block connects to the NoC through an NI. - **Router**: Forwarding element at each network node. Receives flits (flow control units), performs routing table lookup, arbitrates between input ports, and forwards to the output port. Pipeline: 1-3 cycles per hop (routing, arbitration, switch traversal). - **Links**: Physical wires connecting adjacent routers. Width (64-512 bits) determines per-link bandwidth. Wire delay at advanced nodes may require link pipelining (repeater stages between routers). **Topologies** - **2D Mesh**: Standard for tiled architectures (many-core processors). Each router connects to 4 neighbors plus the local IP. Provides multiple paths for fault tolerance and load balancing. XY dimension-order routing is deadlock-free. - **Ring**: Simple topology for moderate endpoint counts (<16). Used in Intel's ring bus (Core i-series). Single path between any pair — bandwidth limited by the ring bisection. - **Hierarchical**: Cluster-level crossbar within a group, mesh/ring between groups. Matches the locality hierarchy of real SoC traffic patterns. **Flow Control** - **Wormhole**: The standard for NoC. A packet is divided into flits; the header flit reserves the route, and body/tail flits follow in a pipeline. Only header flit needs buffering at each hop; body flits flow through reserved channels. Low buffer cost but can cause head-of-line blocking. - **Virtual Channels (VCs)**: Multiple virtual channels share a physical link, each with independent buffering. Prevents head-of-line blocking and enables deadlock-free routing by separating traffic classes. **Quality of Service (QoS)** SoCs have mixed traffic — latency-critical (CPU cache misses, display refresh) and bandwidth-intensive (DMA, video codec). NoC QoS mechanisms (priority-based arbitration, bandwidth reservation, virtual channels per traffic class) ensure real-time deadlines are met despite background traffic. **Network-on-Chip is the communication backbone of modern SoC design** — providing the scalable, modular interconnect fabric that enables hundreds of IP blocks to communicate efficiently while keeping physical design complexity manageable.