on chip power grid ir drop

**On-Chip Power Grid IR Drop** is **the voltage reduction across the metal interconnect power delivery network caused by resistive losses as current flows from package bumps through multiple metal layers to standard cells, directly impacting circuit timing and potentially causing functional failures when supply voltage drops below critical margins**. **Power Grid Architecture:** - **Global Power Grid**: upper metal layers (M10-M15 in advanced nodes) carry power from C4 bumps or micro-bumps through wide, low-resistance stripes—typical metal widths of 5-20 μm with sheet resistance of 5-20 mΩ/sq - **Intermediate Distribution**: middle metal layers (M5-M9) distribute power from global grid to local blocks through via arrays and power straps—via resistance contributes 10-30% of total IR drop - **Local Power Rails**: M1/M2 standard cell power (VDD) and ground (VSS) rails connect directly to transistor source/drain contacts—rail widths of 50-200 nm with sheet resistance of 50-200 mΩ/sq - **Decoupling Capacitors**: on-die decap cells placed in whitespace provide local charge reservoirs—typical density of 100-500 fF/μm² reduces dynamic IR drop by 20-40% **Static IR Drop Analysis:** - **Resistive Network Extraction**: power grid is extracted as a distributed RC network with millions of nodes—each wire segment and via modeled as a resistor, each gate modeled as a current source - **Average Current Model**: each standard cell's average switching and leakage current creates a current demand at its VDD/VSS connection points - **DC Solution**: Kirchhoff's current law solved across the entire power grid network using sparse matrix techniques—identifies worst-case static voltage drop locations - **Target Specification**: static IR drop typically budgeted at <3-5% of nominal VDD (e.g., <25 mV for a 0.75V supply)—violations require adding power stripes, vias, or bump redistribution **Dynamic IR Drop Analysis:** - **Cycle-Accurate Simulation**: vector-based analysis applies realistic switching activity from gate-level simulation—captures simultaneous switching of thousands of gates during clock edges - **Worst-Case Scenarios**: clock tree buffers switching simultaneously with high-activity data paths create peak current demands 5-20x average—dynamic drop can reach 50-100 mV in hotspots - **Resonance Effects**: interaction between on-die capacitance and package inductance creates LC resonance at 100-500 MHz—supply noise amplified at resonance frequency - **Time-Domain Analysis**: transient simulation over multiple clock cycles captures peak droops, overshoots, and settling behavior—time resolution of 1-10 ps required for accuracy **IR Drop Impact on Timing:** - **Cell Delay Sensitivity**: a 10% reduction in VDD increases gate delay by approximately 15-25% in advanced nodes—this consumes timing margin and can cause setup/hold violations - **Clock Skew**: differential IR drop across the clock tree creates voltage-dependent clock arrival times—spatial voltage variation of 20 mV can introduce 10-30 ps of clock skew - **Voltage-Aware STA**: modern timing flows incorporate IR drop maps into static timing analysis—each cell's delay is derated based on its local voltage, providing accurate timing with power integrity effects **On-chip power grid IR drop analysis is essential for guaranteeing that every transistor in the design receives sufficient supply voltage under all operating conditions, as even a small voltage deficit in a critical path can cause timing failures that are difficult to diagnose and expensive to fix after tapeout.**