power grid ir drop

**Power Grid IR Drop and Electromigration Analysis** is the **sign-off verification process that ensures every transistor on the chip receives sufficient supply voltage under worst-case current draw (IR drop) and that every metal wire in the power delivery network can sustain its current density for the chip's rated lifetime without failing from atomic migration (electromigration) — two failure modes that become increasingly critical as supply voltages drop and current densities rise at each process node**. **Static IR Drop** Ohm's law: V_drop = I × R. Current flows from the power pads through progressively narrower metal straps to each standard cell. The cumulative resistive drop reduces the effective supply voltage at the cell. If the local VDD drops below the minimum (typically VDD_nominal - 5-10%), the cell slows down (timing failure) or fails to switch correctly (functional failure). **Dynamic IR Drop** Worse than static: when a large block of logic switches simultaneously (e.g., clock edge, cache line fill), the instantaneous current surge creates both resistive (IR) and inductive (Ldi/dt) voltage drop. The supply voltage rings — dipping below the DC IR-drop level and potentially recovering to overshoot. Dynamic IR drop analysis uses VCD (Value Change Dump) switching activity from representative simulation scenarios to compute the time-domain voltage waveform at every cell. **Analysis Methodology** 1. **Power Grid Extraction**: The PDN (Power Delivery Network) — all VDD/VSS metal straps, vias, package bumps/C4s, and PCB planes — is extracted as an RLC network. 2. **Current Map**: Each standard cell's average and peak current draw is characterized. The spatial current distribution is computed from the placement. 3. **IR Solver**: A linear system solver (RedHawk, Voltus) computes the voltage at every node in the PDN mesh under the specified current load. 4. **EM Check**: Current density through every wire segment and via is compared against foundry-specified maximum current density limits (Jmax). Violations predict accelerated void formation and eventual open-circuit failure. **Electromigration Physics** Current-carrying metal atoms experience a "wind" force from electron momentum transfer. Over time, atoms migrate in the electron flow direction, creating voids (at the cathode end) and hillocks (at the anode end). Black's equation models the MTTF: MTTF = A × J^(-n) × exp(Ea/kT). At 5nm nodes with copper at 105°C, the maximum allowed current density is ~1-2 MA/cm² for 10-year reliability. **Fixing IR/EM Violations** - **Widen Power Straps**: Increase metal width of violating segments to reduce resistance and current density. - **Add Vias**: Parallel vias reduce via resistance (a common IR bottleneck). - **Add Decap Cells**: On-die decoupling capacitors supply charge during transient current spikes, reducing dynamic IR drop. - **Redistribute Power Pads**: Move or add C4 bumps near high-current blocks. - **Reduce Switching Activity**: Clock gating and operand isolation reduce the peak current draw. Power Grid IR Drop and EM Analysis is **the electrical infrastructure verification that guarantees every transistor is properly fed** — because a chip with perfect logic and timing is worthless if the power delivery network starves critical circuits of voltage or crumbles from electromigration after a year in the field.