on chip variation

**On-Chip Variation (OCV)** is a **timing analysis technique that accounts for process, voltage, and temperature variations across different locations on a chip** — recognizing that launch and capture flip-flops do not see identical conditions, requiring pessimistic analysis for robust timing closure. **The OCV Problem** - Standard STA: All cells on a path analyzed at same PVT corner. - Reality: Clock launch path and data capture path traverse different physical regions. - Different regions can have different local Vt, Leff, oxide thickness → different delays. - If launch path is faster than nominal and capture path is slower → setup violation not caught by standard STA. **OCV Derating** - Apply derate factors to cell delays: $T_{derated} = T_{nominal} \times derate$ - Setup analysis: Launch path derated late (+10%), capture path derated early (-10%). - Hold analysis: Launch path derated early (-10%), capture path derated late (+10%). - This is conservative — assumes maximum possible variation between paths. **AOCV (Advanced OCV)** - Standard OCV: Flat derate regardless of cell count. - AOCV insight: Variation averages out for long paths (many cells → closer to mean). - AOCV: Derate depends on path depth and distance between cells. - Long path with 50 cells → small derate (averaging effect). - Short path with 2 cells → large derate (full variation possible). - AOCV requires characterization of derate table vs. depth and distance. **SOCV/LOCV (Statistical / Location-Based OCV)** - Monte Carlo statistical variation models. - LOCV: Cells near each other are correlated (same lithography shot) — less variation between them. - Location-aware pessimism reduction: Adjacent cells get less OCV than cells far apart. **PVT Corners vs. OCV** - PVT corners: Chip-wide variation (SS corner: all slow, FF corner: all fast). - OCV: Within a corner, path-to-path variation. - Both must be analyzed: Run OCV analysis at each PVT corner. **Impact on Timing** - OCV derating can add 5–15% timing pessimism. - AOCV reduces pessimism 3–8% → allows higher frequency or lower power. OCV analysis is **a necessary realism in timing signoff** — ignoring within-die variation leads to chips that meet STA but fail in silicon at process corners, while excessive pessimism leaves performance and area on the table.