On-Resistance

On-resistance is how much a transistor resists current flow when it's fully switched on, and the Ion/Ioff ratio is the spread between that on-state current and the tiny leakage current that still flows when the same transistor is supposed to be off. Together they're the two numbers that actually define how good a transistor is as a switch — a great switch needs on-resistance low enough to pass current efficiently, and an Ion/Ioff ratio high enough that "off" actually means something.

On-Resistance and the Ion/Ioff Ratio V_GS I_D (log scale) I_on — low R_on wanted I_off — leakage Ion / Ioff ratio — the useful dynamic range of the switch Lower R_on moves the top point up; subthreshold leakage control keeps the bottom point down.

On-resistance is simply the transistor's effective resistance in the fully-on state, and it directly sets how much voltage is wasted, and how much power is burned, every time current passes through. A transistor acting as a switch in series with a load behaves like a resistor whose value is R_on while it's on; any current flowing through that resistance produces an I²R power loss and a voltage drop that subtracts from whatever the circuit is trying to deliver downstream. Lower on-resistance means less wasted power and a cleaner on-state voltage, which matters enormously in power-delivery transistors and output drivers where the transistor is carrying real, continuous current rather than just switching a small digital signal.

On-resistance comes from a short list of physical contributors, and each one is a lever process and circuit designers actually pull. The channel itself contributes resistance set by carrier mobility, channel length, and gate drive strength — a wider or shorter channel, or a gate voltage pushed further above threshold, lowers this term. Source and drain contact resistance adds in series with the channel and has become a bigger fraction of total on-resistance at advanced nodes, which is exactly why foundries invest in better silicide contacts and epitaxially-grown source/drain shapes. Parasitic routing resistance in the metal layers connecting the transistor to the rest of the circuit adds a third term that layout engineers manage through wire width and via count rather than device physics.

Ioff is the current that leaks through a transistor that's supposed to be fully off, and in practice it's never actually zero. Subthreshold conduction lets some current trickle through even below threshold voltage, and short-channel effects like DIBL make that leakage worse as supply voltage rises. Gate-oxide tunneling and junction leakage add further small contributions. None of these individually look large, but multiplied across the billions of transistors on a modern chip, aggregate Ioff leakage is a major and sometimes dominant contributor to a chip's standby power — which is why so much process and circuit-design effort goes into keeping this one number small.

The Ion/Ioff ratio is the real figure of merit for how good a transistor is as a digital switch, independent of either current in isolation. A transistor could have enormous on-current and still be a poor switch if its off-current is also large, because the circuit would struggle to tell "clearly on" apart from "clearly off." Modern logic transistors target Ion/Ioff ratios of many orders of magnitude — a huge dynamic range between the on-state and off-state currents — precisely so that downstream logic can reliably distinguish the two states even with normal manufacturing variation and temperature swings layered on top.

On-resistance and Ion/Ioff pull against each other through nearly every lever available to a circuit or process designer, which is why neither number can simply be optimized in isolation. Raising gate drive voltage lowers on-resistance but increases power and, at the margins, stresses gate reliability. Shrinking channel length lowers on-resistance by shortening the conduction path but worsens short-channel effects and raises leakage, directly hurting Ion/Ioff. Techniques that genuinely improve both at once — strained channels that boost mobility without touching leakage, or FinFET/gate-all-around architectures that improve gate control enough to shrink channel length without the usual leakage penalty — are exactly why those innovations were considered big enough wins to justify the manufacturing complexity they added.

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