opc computational lithography
**Computational Lithography** is the **collection of simulation and optimization techniques that modify mask patterns to compensate for optical and process distortions during lithographic patterning** — where algorithms including OPC (Optical Proximity Correction), ILT (Inverse Lithography Technology), and SMO (Source-Mask Optimization) transform the intended design shapes into mask shapes that, after passing through the optical system, will print the correct features on the wafer.
**Why Computational Lithography?**
- At sub-wavelength patterning (feature size << 193 nm): Optical proximity effects cause pattern distortion.
- A simple rectangular mask feature does NOT print as a rectangle on the wafer — corners round, lines narrow, spaces widen.
- Without correction: CD errors of 20-50% → chip doesn't function.
- With OPC: Mask shapes pre-distorted so wafer image matches design intent.
**Key Techniques**
| Technique | What It Does | Complexity |
|-----------|-------------|------------|
| Rule-Based OPC | Add serifs, biases based on rules | Low |
| Model-Based OPC | Simulate imaging → iteratively adjust mask | High |
| ILT (Inverse Litho) | Compute optimal mask from desired wafer image | Very High |
| SMO | Co-optimize illumination source + mask | Very High |
| SRAF Placement | Add sub-resolution assist features | Medium |
**Optical Proximity Correction (OPC)**
- **Rule-based**: "If line end is within 50 nm of another → add 10 nm hammerhead serif."
- **Model-based**: Full lithographic simulation (Hopkins diffraction model) predicts printed image → iterative edge adjustment until simulated image matches target.
- Typical OPC: Each edge of each polygon adjusted independently → billions of edge movements per chip.
**Inverse Lithography Technology (ILT)**
- Formulate mask design as optimization problem: Find mask that minimizes |wafer_image - target|.
- Result: **Curvilinear** mask shapes — organic, free-form contours.
- Curvilinear masks print better than Manhattan (rectilinear) OPC shapes.
- Challenge: Curvilinear masks harder to write with mask writers → multi-beam mask writers enable ILT.
**Source-Mask Optimization (SMO)**
- Jointly optimize the scanner illumination pupil shape AND the mask pattern.
- Custom illumination (freeform source) tailored per design layer.
- 5-10% improvement in process window over OPC alone.
**Computational Cost**
- Full-chip OPC for a single layer: **10,000-100,000 CPU-hours**.
- Requires massive compute farms (1,000+ servers).
- GPU acceleration: Emerging use of GPU clusters for litho simulation → 10x speedup.
- ML-assisted OPC: Neural networks predict corrections → faster iteration.
**SRAF (Sub-Resolution Assist Features)**
- Small features added near main features on the mask — too small to print themselves.
- Improve aerial image contrast and depth of focus of the main features.
- Placement optimized by model-based or ILT algorithms.
Computational lithography is **what makes sub-wavelength patterning possible** — without these algorithms, semiconductor manufacturing would have reached its resolution limit decades ago, and the continuation of Moore's Law is as much a computational achievement as a materials and optics one.