optical proximity correction
**Optical Proximity Correction (OPC)** is a **computational lithography technique that systematically modifies photomask features — adding serifs, biasing line widths, and inserting sub-resolution assist features (SRAFs) — to pre-compensate for optical diffraction and process effects** so that the printed wafer pattern closely matches the intended design, a critical enabling technology for patterning features much smaller than the exposure wavelength.
When light passes through a photomask, diffraction causes the aerial image to differ from the mask pattern: line ends shorten (line-end pullback), corners round, and isolated features print differently from dense features (iso-dense bias). At the 193nm DUV wavelength used for most patterning (even at 5nm node via multi-patterning), minimum features are 30-50nm — far below the wavelength, making these optical proximity effects severe.
**Types of OPC:**
**Rule-based OPC**: Simple, deterministic corrections based on lookup tables:
- Add serifs at corners to prevent rounding
- Bias line widths based on pitch (wider for isolated, narrower for dense)
- Apply fixed line-end extensions
- Fast but insufficient for advanced nodes
**Model-based OPC (MBOPC)**: Iterative, simulation-driven correction:
```
1. Start with target design pattern
2. Simulate the lithographic process (optical + resist + etch models)
3. Compare simulated wafer image with target → compute edge placement error (EPE)
4. Adjust mask features to reduce EPE
5. Re-simulate and iterate until EPE < spec (typically <1nm)
6. Add SRAFs (sub-resolution assist features) to improve process window
```
The simulation models include: **optical model** (Hopkins/Abbe formulation of partially coherent imaging, including pupil aberrations and source shape), **resist model** (chemical amplification, acid diffusion, development kinetics), and **etch model** (pattern-dependent etch bias). Model accuracy (model-to-silicon correlation) must be <1nm for production use.
**Sub-Resolution Assist Features (SRAFs)**:
SRAFs are thin lines placed next to isolated features on the mask that are too narrow to print on the wafer themselves but modify the diffraction pattern to make the isolated feature print as if it were in a dense array — equalizing the iso-dense bias and improving depth of focus.
**Inverse Lithography Technology (ILT)**:
The most advanced form treats mask optimization as a mathematical inverse problem — directly compute the optimal mask pattern that produces the desired wafer image, without starting from the design shapes. ILT produces freeform 'curvilinear' mask shapes that outperform edge-based OPC but generate extremely complex mask patterns requiring multi-beam mask writers.
**Computational Requirements:**
OPC for a single advanced mask layer requires processing billions of features. A full chip OPC run takes 10-100+ hours on clusters of thousands of CPU cores. Major EDA vendors (Synopsys, Siemens/Mentor, Cadence) provide OPC tools. GPU acceleration is increasingly adopted to reduce runtimes.
**For EUV lithography**, OPC is simpler because the 13.5nm wavelength provides better native resolution, but stochastic effects (shot noise) introduce new correction challenges (SOCS — stochastic-OPC). Mask 3D effects (thick absorber) also require rigorous electromagnetic simulation.
**OPC is one of the most computationally intensive steps in semiconductor manufacturing** — without systematic mask correction, no advanced-node device could be manufactured, making computational lithography a fundamental pillar of modern semiconductor technology that consumes more compute per tapeout than the chip design itself.