oxide cmp

Oxide CMP polishes silicon dioxide and other dielectric films to achieve planar surfaces required for multilevel interconnect fabrication, used primarily for shallow trench isolation (STI) planarization and interlayer dielectric (ILD) planarization in semiconductor manufacturing. For STI CMP, oxide deposited to fill isolation trenches is polished back to the silicon nitride hard mask, using the nitride as a polish stop layer. Slurries are typically ceria-based (CeO₂) or silica-based (SiO₂) with high oxide-to-nitride selectivity (50:1 to 100:1 for ceria slurries). For ILD CMP, deposited oxide (TEOS, HDP, or PECVD oxide) over patterned metal layers is planarized to create a flat surface for the next interconnect level. ILD CMP uses silica-based slurries at pH 10-11 with removal rates of 2000-4000 Å/min. Key process parameters include downforce (1-5 psi), platen speed (60-120 RPM), slurry flow rate (100-300 mL/min), and pad conditioning. Critical challenges include pattern-dependent polishing rates (erosion in dense areas, dishing in wide features), within-wafer non-uniformity (WIWNU target < 3%), and defect generation (scratches from agglomerated slurry particles or pad debris). Multi-zone pressure control on the carrier head compensates for edge-to-center removal rate variations. Endpoint detection uses motor current monitoring, optical interferometry, or eddy current sensing.