package yield

**Package Yield** is the **fraction of known-good die (KGD) that survive the packaging process and emerge as functional packaged devices** — measuring the success rate of die attach, wire bonding or flip-chip bumping, underfill, encapsulation, and other packaging steps. **Package Yield Loss Sources** - **Die Attach**: Voids in die attach adhesive — cause thermal hotspots and delamination. - **Wire Bonding**: Bond lift-off, wire sweep, ball bond cracking — electrical open circuits. - **Flip-Chip**: Bump bridging (shorts), non-wet opens, underfill voids — solder joint reliability failures. - **Encapsulation**: Mold compound voids, delamination, warpage — mechanical protection failures. **Why It Matters** - **Impact**: Package yield loss directly wastes fully processed wafer die — the most expensive inventory in the fab. - **Advanced Packaging**: Chiplet-based packaging (CoWoS, EMIB) has more assembly steps — package yield is increasingly critical. - **Target**: Mature packaging processes achieve >99% package yield — but advanced packages may be lower. **Package Yield** is **surviving the packaging step** — the fraction of good die that successfully become functional packaged devices.