packaging substrate

**Advanced Packaging Substrate Technology (ABF, Glass Core)** is **the high-density interconnect (HDI) substrate platform that routes signals between the fine-pitch bumps of an advanced IC package and the coarser-pitch solder balls that connect to the printed circuit board** — packaging substrates have become a critical bottleneck and differentiator as chiplet-based architectures demand ever-finer line and space (L/S) geometries. - **ABF Build-Up Film**: Ajinomoto Build-up Film (ABF) is a glass-fiber-free epoxy dielectric laminated in successive layers to build up the substrate routing. Its smooth surface (Ra < 0.2 µm) enables semi-additive process (SAP) copper patterning at L/S down to 8/8 µm currently, with roadmaps targeting 2/2 µm. ABF's low dielectric constant (~3.3) and loss tangent (~0.01) support high-speed signaling. - **Semi-Additive Process (SAP)**: ABF layers are metalized by electroless Cu seeding, photoresist patterning, electrolytic Cu plating, resist strip, and seed etch. SAP produces finer lines than subtractive etching and is the standard process for advanced build-up substrates. Modified SAP (mSAP) using ultra-thin copper foil is used for intermediate density. - **Core Materials**: Conventional substrates use BT (bismaleimide triazine) resin cores with glass-fiber reinforcement for rigidity and CTE matching. Core thickness is typically 200–800 µm, with laser-drilled through-core vias connecting top and bottom routing. - **Glass-Core Substrates**: Glass offers superior dimensional stability (CTE ~3.2 ppm/°C, matching silicon), excellent surface smoothness for fine-line patterning, and through-glass vias (TGV) enabling high wiring density. Glass cores can be thinned to 100 µm, reducing substrate warpage and total package height. Major substrate suppliers are actively qualifying glass-core technology for HPC chiplet packages. - **Via Technology**: Laser-drilled microvias (50–75 µm diameter) connect build-up layers. Stacked vias increase routing density but require reliable copper fill. Through-core vias may be mechanically drilled (for BT) or laser/etch processed (for glass). - **Warpage Management**: As substrate size grows to accommodate large chiplet assemblies (> 55 × 55 mm), CTE mismatch between ABF, copper, and core causes warpage during solder reflow. Symmetric build-up stackups, stiffener frames, and simulation-guided design mitigate warpage. - **Signal Integrity**: At data rates exceeding 100 Gb/s per lane (e.g., for 224G SerDes), substrate dielectric loss, impedance discontinuities, and via stub resonance critically impact channel performance. Low-loss dielectrics and optimized via anti-pad geometries are required. - **Supply and Cost**: ABF film supply has been constrained by booming demand for AI/HPC chip packages. A single large HPC substrate can cost $50–150, representing a significant fraction of total package cost. Advanced packaging substrates are evolving from a commodity interconnect layer into a high-technology platform where dielectric material science, fine-line metallization, and precision via formation define the limits of heterogeneous integration.