through glass via
**Through-Glass Via (TGV) Technology** is the **advanced packaging approach using glass substrates with laser-drilled vertical interconnects** — offering superior electrical properties (low dielectric constant ~5, low loss tangent) compared to silicon interposers, larger panel-compatible form factors, and better dimensional stability than organic substrates, making glass a compelling interposer and substrate material for high-performance computing, RF applications, and next-generation chiplet integration.
**Why Glass Substrates**
| Property | Silicon Interposer | Organic Substrate | Glass Substrate |
|----------|-------------------|------------------|----------------|
| Dielectric constant | 11.7 | 3.5-4.5 | 4.6-5.4 |
| Loss tangent | 0.01-0.02 | 0.01-0.02 | 0.002-0.005 |
| CTE (ppm/°C) | 2.6 | 12-17 | 3.2-8.0 (tunable) |
| Dimensional stability | Excellent | Poor (warpage) | Excellent |
| Wafer/panel size | 300mm round | 510×515mm+ | 300mm round or panel |
| Cost | High (Si wafer) | Medium | Low-Medium |
| Thickness | 50-100 µm | 400-800 µm | 100-300 µm |
**CTE Advantage**
- Silicon die CTE: ~2.6 ppm/°C.
- Organic substrate CTE: ~15 ppm/°C → large mismatch → warpage, solder joint stress.
- Glass CTE: 3.2-8.0 ppm/°C (tunable by composition) → better match to silicon.
- Result: Less warpage, more reliable solder joints, thinner packages possible.
**TGV Formation Process**
```
[Glass substrate (100-300 µm thick)]
↓
Step 1: Via formation
- Laser drilling (excimer UV or ultrafast femtosecond)
- Via diameter: 20-100 µm
- Via pitch: 50-200 µm
- Aspect ratio: up to 10:1
↓
Step 2: Via metallization
- Seed layer: PVD TiCu or electroless Cu
- Cu electroplating (conformal or filled)
- Via fill options: Full copper fill or conformal with polymer fill
↓
Step 3: RDL formation
- Dielectric (polymer or inorganic)
- Lithography, via etch, Cu plating
- Multiple RDL layers (2-6)
↓
Step 4: Die attach and assembly
- Chiplets bonded to glass interposer
- Interposer attached to package substrate or PCB
```
**Via Formation Methods**
| Method | Via Diameter | Speed | Quality |
|--------|-------------|-------|--------|
| UV excimer laser | 20-100 µm | Medium | Good |
| Femtosecond laser | 5-50 µm | Slow | Excellent (no cracking) |
| Photo-etchable glass (APEX) | 10-100 µm | Fast (batch) | Good |
| Sandblasting | 50-200 µm | Fast | Rough sidewalls |
**Applications**
| Application | Why Glass Is Preferred |
|------------|----------------------|
| 2.5D interposer (alternative to Si) | Lower cost, better RF, larger size |
| Glass core BGA substrate | Better dimensional stability than organic |
| 5G/mmWave packaging | Low dielectric loss at high frequency |
| Photonics interposer | Transparent to optical signals |
| Medical/bio MEMS | Biocompatible, optically transparent |
**Industry Status**
| Company | Focus | Status |
|---------|-------|--------|
| Intel | Glass core substrates for CPUs | Announced 2023, production ~2026-2028 |
| Corning | Glass wafer/panel supply | Materials supplier |
| SKC (Absolics) | Glass interposer panels | Pilot production |
| AGC (Asahi Glass) | Glass for semiconductor | Material development |
| Samsung | Glass substrate evaluation | R&D |
**Challenges**
| Challenge | Issue | Mitigation |
|-----------|-------|------------|
| Glass fragility | Brittle, breaks during handling | Edge strengthening, carrier support |
| Via drilling throughput | Laser drilling is slow for high via count | Multi-beam laser, photo-etchable glass |
| Cu adhesion to glass | Poor inherent adhesion | Adhesion layers (Ti, TiW, Cr) |
| Thermal conductivity | Glass: 1 W/mK vs. Si: 150 W/mK | Thermal vias, metal heat spreaders |
Through-glass via technology is **the emerging substrate revolution that combines the electrical precision of silicon interposers with the cost advantages of panel-level manufacturing** — Intel's announcement of glass core substrates for future processors signals that glass is transitioning from an academic curiosity to a production reality, potentially reshaping the semiconductor packaging industry with superior signal integrity, dimensional stability, and cost scalability.