parallel

**Parallel Programming Memory Consistency Models** is **a formal specification of guarantees about memory access ordering across threads/processes, defining what memory values threads observe given particular access patterns** — critical for correctness of concurrent programs and performance optimization. Memory model defines allowable behavior. **Sequential Consistency** Lamport's model: memory behaves as single shared variable, access interleaving is some sequential order. Strongest guarantee: threads observe consistent state. Naive implementation serializes all accesses. Most restrictive, easiest to reason about. **Relaxed Memory Models** relax sequential consistency for performance. Allow some reordering, reducing synchronization barriers. **Store Buffering and Visibility Delays** processors maintain write buffers. Writes don't immediately visible to other processors—visibility delayed until buffer flushed (explicit sync) or timeout. Reordering: Load-Load, Load-Store, Store-Store, Store-Load. **Release and Acquire Semantics** synchronization primitive types: release writes make prior memory operations visible, acquire reads ensure subsequent operations see released writes. Release-acquire pairs form synchronization points. Other memory operations not constrained. **Weakly-Ordered Models** treat reads and writes differently. Write (release) and read (acquire) synchronization, but unsynchronized reads/writes may reorder. **Java Memory Model** includes happens-before relations: synchronized operations establish happens-before edges. All accesses before synchronized operation happen before accesses after. Volatile reads/writes introduce memory barriers. **C++ Memory Model** atomic operations with memory_order specifiers: memory_order_relaxed (no sync), memory_order_release/acquire (sync), memory_order_seq_cst (sequential consistency). **Data Races and Safety** data race: unsynchronized read/write to same variable. Many models promise no data races enables optimizations (compiler reordering, cache coherence optimizations). **Lock-Based Synchronization** mutual exclusion (mutex) ensures only one thread executes critical section. Acquire lock establishes happens-before with previous lock release. **Hardware Memory Barriers** CPU instructions (mfence, lwsync) enforce ordering when model doesn't provide ordering. Necessary for cross-processor synchronization. **Performance vs. Correctness Trade-off** strong memory models (sequential consistency) limit optimization. Weak models enable aggressive optimizations but require careful synchronization. **Porting Between Architectures** code using assumed memory model may fail on weaker hardware. Explicit synchronization necessary for portability. **Applications** include lock-free data structures, concurrent algorithms, real-time systems. **Understanding memory models is essential for writing correct concurrent programs and understanding performance behavior** on multi-processor systems.