parametric yield analysis
**Parametric yield analysis** is the **evaluation of chip pass rate against continuous electrical specification limits such as speed, leakage, and noise margins** - unlike catastrophic defect yield, it focuses on performance spread and limit violations caused by process variation.
**What Is Parametric Yield?**
- **Definition**: Fraction of units meeting all parametric specs at test conditions.
- **Typical Parameters**: Frequency targets, standby current, drive current, offset, and timing margins.
- **Failure Type**: Soft fails where silicon is functional but out of allowable range.
- **Analysis View**: Distribution overlap with spec windows and guardbands.
**Why Parametric Yield Matters**
- **Revenue Impact**: Parametric tails drive binning loss and lower-value product mix.
- **Design Margin Cost**: Overly tight limits or weak variation control reduce sellable die count.
- **Process Prioritization**: Highlights which parametric contributors dominate yield loss.
- **Test Strategy Link**: Enables adaptive screening and smarter bin thresholds.
- **Customer Quality**: Maintains delivered performance consistency across lots.
**How It Is Analyzed**
**Step 1**:
- Collect distribution data from simulation and wafer sort for each critical parameter.
- Fit statistical models including correlation and temperature-voltage dependency.
**Step 2**:
- Compute pass probability for each spec and joint yield across all constraints.
- Identify limit-sensitivity hotspots and optimize guardbands or design settings.
Parametric yield analysis is **the practical framework for turning distribution tails into clear yield-improvement actions** - it bridges electrical performance variability with product-grade economics.