semiconductor parametric test

**Parametric Testing (E-Test)** is the **inline quality monitoring methodology that measures fundamental electrical parameters of semiconductor devices on dedicated test structures distributed across the wafer — verifying that transistor threshold voltage, leakage current, sheet resistance, contact resistance, capacitance, and dozens of other parameters fall within specification limits to detect process drift, excursions, and systematic defects before committing to expensive back-end processing**. **Why Parametric Testing Is Essential** Semiconductor manufacturing involves 500-1000+ processing steps. Physical inspection (optical, SEM) catches visible defects but cannot detect electrical failures — a gate oxide 0.3nm too thin looks identical to a good one under a microscope but causes catastrophic leakage. Parametric testing measures the electrical consequences of process variations, providing direct feedback on whether the wafer will yield functional chips. **Test Structures** - **PCM (Process Control Monitor) Sites**: Dedicated areas in the scribe lanes (the gaps between dies that are cut during dicing) containing hundreds of individual test structures. Each wafer has 5-20 PCM sites at standardized locations. - **Structure Types**: - **Transistors**: Measure Vth (threshold voltage), Ion (drive current), Ioff (leakage current), gm (transconductance) for NMOS and PMOS at multiple channel lengths and widths. - **Resistors**: Van der Pauw structures for sheet resistance of each interconnect metal layer, polysilicon, diffusion, silicide, and well implants. - **Kelvin Contacts/Vias**: Four-terminal resistance measurement of contact and via resistance for each metal-to-metal connection, isolating contact resistance from line resistance. - **Capacitors**: Metal-insulator-metal and MOS capacitor structures measuring dielectric thickness and quality. - **Diodes**: Junction leakage measurement for n-well/p-substrate and p-well/n-well junctions. - **Ring Oscillators**: Functional circuit at minimum pitch that measures gate delay (speed grade) directly. **Measurement Flow** Parametric testing occurs at key milestones: 1. **After STI/Well Formation**: Junction depths, well resistance, isolation leakage. 2. **After Gate Stack**: Gate oxide thickness (Capacitance-Voltage), threshold voltage, drive current. 3. **After Contact/Metal 1**: Contact resistance, M1 sheet resistance. 4. **After Final Metal**: All interconnect layers, full transistor I-V characteristics, ring oscillator frequency. 5. **WAT (Wafer Acceptance Test)**: Final comprehensive parametric test before wafer shipment. **Statistical Process Control** Parametric data feeds SPC charts that track each parameter over time. Spec limits define the acceptable range. Control limits (tighter than spec) trigger engineering review. Systematic shifts indicate process drift (e.g., implant dose trending high), while sudden excursions indicate equipment failures (e.g., contaminated chemical bath). The correlation between parametric values and final die yield is the foundation of yield modeling. Parametric Testing is **the electrical conscience of the fab** — translating invisible atomic-scale process variations into measurable voltages and currents that tell engineers whether their transistors, contacts, and interconnects are performing as designed.