wafer acceptance test
**Wafer Acceptance Test (WAT)** is the **electrical measurement of test structures fabricated alongside production chips to monitor process health and detect manufacturing excursions** — providing per-wafer parametric data (threshold voltage, leakage, resistance, capacitance) that determines whether a wafer meets specifications before proceeding to die-level testing.
**What WAT Measures**
- **Transistor Parameters**: Vt (threshold voltage), Ion (drive current), Ioff (leakage), gm (transconductance).
- **Dielectric Parameters**: Breakdown voltage, leakage current density, capacitance per area.
- **Interconnect Parameters**: Sheet resistance (Rs), contact resistance (Rc), via resistance.
- **Device Parameters**: Ring oscillator frequency, SRAM Vmin, matched pair Vt mismatch.
**Test Structure Location**
- **Scribe Line (Kerf)**: Test structures placed in the dicing lane between dies — sacrificed during wafer saw.
- Typical: 60-200 μm wide scribe lane.
- Contains 50-500+ test structures per module.
- **In-Die PCM**: Some test structures placed inside die area for spatial uniformity monitoring.
**WAT Flow**
1. **Process Completion**: Wafer completes all FEOL + BEOL processing.
2. **Probe**: Automated probe card contacts test structure pads.
3. **Measurement**: Parametric analyzer (Keithley 4200, Form Factor) measures I-V, C-V curves.
4. **Data Analysis**: Results compared against specification limits (mean ± 3σ or tighter).
5. **Disposition**: Pass → proceed to die test. Fail → wafer held for engineering review or scrapped.
**Key WAT Parameters by Process Module**
| Module | Parameter | Typical Spec |
|--------|-----------|-------------|
| FEOL Transistor | NMOS Vt | Target ± 20 mV |
| FEOL Transistor | NMOS Idsat | > X μA/μm |
| Gate Oxide | Breakdown Voltage | > Y V |
| Contact | Rc (contact resistance) | < Z Ω |
| Metal 1 | Sheet Resistance | Target ± 5% |
| Via | Via chain resistance | < W Ω/via |
**WAT vs. Production Test**
- **WAT**: Tests process quality (is the silicon good?). Done on test structures.
- **Production Test (ATE)**: Tests die functionality (does this chip work?). Done on actual products.
- WAT flags process problems before expensive die-level testing wastes time on bad wafers.
Wafer acceptance testing is **the quality gate of semiconductor manufacturing** — it catches process excursions early, enables statistical process control, and provides the parametric data engineers need to tune and optimize every module in the fabrication flow.