parasitic extraction

**Parasitic Extraction** — computing the resistance (R) and capacitance (C) of every wire and via in a chip layout, essential for accurate timing and power analysis. **Why Extraction?** - Wires are not ideal — they have resistance (slows signals) and capacitance (stores charge) - At advanced nodes, interconnect RC delay dominates over transistor delay - Without extraction, timing analysis is meaningless **What Is Extracted** - Wire resistance (proportional to length/width) - Wire-to-wire coupling capacitance (causes crosstalk) - Wire-to-ground capacitance - Via resistance (can be significant for long via stacks) **Extraction Types** - **RC (typical)**: Resistance and capacitance network - **RCC (with coupling)**: Includes capacitive coupling between adjacent wires (for crosstalk analysis) - **RLC**: Includes inductance (for high-speed I/O and power grid analysis) **Flow** 1. Extract parasitics from layout → SPEF file (Standard Parasitic Exchange Format) 2. Feed SPEF into STA tool for accurate timing 3. Feed into power analysis for accurate switching power **Tools**: Synopsys StarRC, Cadence Quantus, Siemens xACT **Parasitic extraction** is the bridge between physical design and signoff — it translates geometry into electrical reality.