path delay fault

**Path Delay Fault** is a **comprehensive timing fault model that tests the cumulative propagation delay along an entire sensitizable path** — from a primary input (or flip-flop output) to a primary output (or flip-flop input). **What Is a Path Delay Fault?** - **Model**: The total delay along a specific path $PI ightarrow G_1 ightarrow G_2 ightarrow ... ightarrow PO$ exceeds the clock period. - **Challenge**: The number of paths in a circuit is exponential ($2^N$ for $N$ reconvergent gates). - **Critical Paths**: In practice, only the longest (timing-critical) paths are tested. - **Detection**: Requires robust sensitization (all side inputs must be non-controlling). **Why It Matters** - **Complete Timing Coverage**: Catches small distributed delays that transition fault testing misses. - **Design Correlation**: Directly maps to Static Timing Analysis (STA) critical paths. - **Limitation**: Exponential path count makes exhaustive testing impractical. **Path Delay Fault** is **the ultimate timing audit** — testing the end-to-end speed of the silicon's most critical signal highways.