photodetector

**Photodetector.** converts incident optical energy into an electrical quantity such as current, voltage, resistance, or a discrete count. A receiver is not characterized by responsivity alone: wavelength, quantum efficiency, bandwidth, capacitance, dark current, noise-equivalent power, saturation, linearity, gain, active area, bias, temperature, package and following electronics determine what signal can be recovered. Semiconductor photodiodes dominate high-speed links, while avalanche and single-photon devices add internal gain at the cost of bias and statistical noise. A defensible specification states signal range, source and load impedance, supply, process, voltage and temperature corners, frequency or wavelength band, modulation, duty cycle, target error probability, allowed calibration, startup behavior, lifetime, area, package, and measurement reference plane. A headline value without these conditions is not portable. Gain, loss, bandwidth, noise, distortion, efficiency, jitter, drift, and power interact through device physics and feedback; improving one can move the limiting mechanism into bias, matching, parasitics, interconnect, thermal behavior, or packaging. **Physical principles and architectures.** A reverse-biased PIN photodiode absorbs photons in a depleted intrinsic region. Each photon above the gap may create an electron–hole pair; the electric field sweeps carriers to contacts, producing photocurrent. Transit time and RC loading limit speed. An avalanche photodiode uses impact ionization for internal multiplication, improving receiver sensitivity when multiplication gain outweighs added excess noise. A SPAD operates above breakdown and registers an avalanche from a single carrier, then requires quenching and a dead time. Phototransistors add current gain but sacrifice speed and linearity; bolometers sense heating over broad spectra. Models must cover the operating region rather than only a nominal small-signal point. The hierarchy links material and device behavior, compact models, extracted layout, package and board or optical coupling, control logic, and the end-to-end channel. Corners expose systematic shifts; Monte Carlo analysis exposes local mismatch; transient noise or phase-noise analysis exposes timing and spectral uncertainty. Model correlation uses dedicated structures and separates intrinsic response from pads, cables, fixtures, probes, fibers, connectors, de-embedding, and instrumentation limits. **Circuit, device, and process implementation.** Material choice follows wavelength and integration: silicon serves visible and selected near-infrared bands, germanium extends silicon photonics toward telecom wavelengths, InGaAs is common in near-infrared receivers, and compound or narrow-gap materials cover longer wavelengths. Waveguide-coupled detectors trade area for interaction length and integrate naturally with photonic circuits. Layout minimizes capacitance and leakage while shielding optical and electrical crosstalk. SPAD arrays add quench circuits, time-to-digital converters, gating, histogram memory, calibration, and logic that can dominate area and power. Implementation closes a loop between architecture, schematic, layout, process, package, and calibration. Floorplanning protects sensitive nodes from digital return currents, substrate coupling, supply bounce, thermal gradients, stress, and aggressor routing. Symmetry and common-centroid placement help only when orientation, surroundings, contacts, vias, density fill, gradients, and routing parasitics are also controlled. Optical interfaces add sidewall roughness, mode mismatch, polarization and wavelength sensitivity; RF interfaces add transmission-line discontinuity, radiation, ground return, and launch design. **Applications and system trade-offs.** PIN receivers serve Ethernet, datacenter, coherent-monitoring, and analog optical links; APDs extend link or lidar sensitivity; SPADs enable time-of-flight lidar, fluorescence lifetime, quantum communication, and low-light imaging; CMOS image sensors use pixel photodiodes; spectroscopy and thermal imaging use wavelength-specific structures. The link budget must include coupling and propagation loss, transmitter extinction and noise, detector saturation, TIA noise, bandwidth, equalization, decision threshold, background light, optical filter, temperature, and target error probability. System evaluation includes every driver, bias network, converter, clock, termination, coupler, package transition, control loop, monitor, calibration cycle, and fallback. Report useful throughput or signal quality at the required error rate and environment, not an isolated device maximum. Production readiness also needs test time, observability, repair or trim strategy, lot and wafer distributions, guard bands, yield learning, firmware ownership, supply-chain constraints, and a way to diagnose drift after deployment. | Detector | Operating mode | Internal gain | Speed / sensitivity character | Representative use | |---|---|---|---|---| | PIN photodiode | Reverse-biased depletion collection | Unity | Fast, linear, low excess noise | Fiber receiver, monitor | | APD | Below-breakdown avalanche multiplication | Moderate | Higher sensitivity with excess noise and high bias | Longer links, lidar | | SPAD | Geiger mode above breakdown | Digital avalanche event | Single-photon sensitivity with dead time | Time-of-flight, quantum, low light | | Phototransistor | Photodiode driving transistor action | Current gain | High responsivity, lower speed and linearity | Sensors and isolation | ```svg ``` **Verification, characterization, and reliability.** Measurements sweep wavelength, optical power, bias, frequency and temperature to extract responsivity, quantum efficiency, dark current, capacitance, bandwidth, impulse response, linearity, saturation, noise, and detectivity. APD tests include gain, breakdown distribution and excess-noise factor; SPAD tests include photon-detection probability, dark-count rate, afterpulsing, crosstalk, dead time, timing jitter and pileup. Reliability covers optical overload, high field, humidity, surface leakage, radiation where relevant, thermal cycling, package contamination, fiber alignment, ESD, and calibration stability. Verification combines operating-point checks, AC and noise analysis, large-signal transient tests, periodic steady-state where appropriate, corner and mismatch sweeps, extracted-layout simulation, electromagnetic or optical simulation, and behavioral co-simulation with control logic. Benchtop or wafer tests use traceable calibration, documented uncertainty, stable bias and temperature, guard structures, standards, and raw-data retention. Stress tests cover maximum ratings, ESD, latch-up where applicable, electrical overstress, hot carriers, dielectric wear, electromigration, optical power, humidity, thermal cycling, mechanical strain, and aging of calibration. A defensible specification states signal range, source and load impedance, supply, process, voltage and temperature corners, frequency or wavelength band, modulation, duty cycle, target error probability, allowed calibration, startup behavior, lifetime, area, package, and measurement reference plane. A headline value without these conditions is not portable. Gain, loss, bandwidth, noise, distortion, efficiency, jitter, drift, and power interact through device physics and feedback; improving one can move the limiting mechanism into bias, matching, parasitics, interconnect, thermal behavior, or packaging. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.