physical aware synthesis
**Physical-Aware Synthesis** is the **logic synthesis methodology that incorporates physical layout information (wire lengths, placement, congestion) during the optimization process** — producing netlists that are inherently better suited for placement and routing, reducing the gap between synthesis estimates and final physical implementation timing.
**The Problem with Traditional Synthesis**
- Traditional synthesis uses **wire load models** (statistical estimates of wire capacitance based on fanout).
- Wire load models are inaccurate: Actual wire delay depends on physical distance, not just fanout count.
- Result: Synthesis reports show timing clean, but after placement → many timing violations appear.
- **"The timing wall"**: Large design effort spent fixing post-placement timing that synthesis didn't predict.
**How Physical-Aware Synthesis Works**
1. **Floorplan Import**: Synthesis tool reads the floorplan (block placement, pin locations, routing channels).
2. **Virtual Placement**: Tool performs a quick trial placement of cells during synthesis.
3. **Wire Delay Estimation**: Uses actual estimated wire lengths (based on virtual placement) instead of wire load models.
4. **Optimization Loop**: Logic optimization, technology mapping, and sizing decisions account for physical wire delays.
5. **Congestion Awareness**: Tool identifies routing-dense areas and avoids creating more logic there.
**Tool Implementations**
| Tool | Vendor | Approach |
|------|--------|---------|
| Design Compiler Topographical | Synopsys | Built-in placer during synthesis |
| Design Compiler NXT | Synopsys | Next-gen with enhanced physical awareness |
| Genus Synthesis | Cadence | Physical-aware with iSpatial technology |
| RTL Compiler Physical | Cadence (legacy) | Early physical synthesis |
**Benefits**
- **Timing correlation**: Post-synthesis timing matches post-P&R timing within 5-10% (vs. 20-30% with wire load models).
- **Fewer iterations**: Reduced back-and-forth between synthesis and P&R teams.
- **Better QoR**: Physical awareness enables placement-aware buffering, logical restructuring, and cell sizing.
- **Congestion reduction**: 10-20% reduction in routing DRC violations.
**In Modern Flows**
- Physical-aware synthesis is **standard practice** at 28nm and below.
- At 5nm/3nm: Some teams skip traditional synthesis entirely → use **concurrent optimization** where synthesis and placement run as a unified engine (Fusion Compiler, Innovus).
Physical-aware synthesis is **the bridge between logical design and physical implementation** — by incorporating real-world wire delays during logic optimization, it eliminates the systematic timing prediction errors that were the #1 source of design closure pain in traditional RTL-to-GDSII flows.