physical design routing

**Physical Design Routing** is the **final, agonizing physical implementation phase where Electronic Design Automation (EDA) tools weave miles of microscopic copper and via connections through a massively constrained 3D labyrinth of metal layers to connect millions of placed standard cells without breaking timing, power, or manufacturing design rules**. **What Is Routing?** - **The Objective**: Connecting the input and output pins of every logic gate exactly as specified in the synthesized netlist. - **Global Routing**: The coarse-grained pathfinding phase. The chip is divided into a grid, and the router assigns rough pathways (like deciding to take Highway 101 to I-280) to avoid overloading any specific region (congestion). - **Detailed Routing**: The microscopic, exact assignment of metal tracks and vias. It physically draws the exact rectangles of copper on Metal 1, Metal 2, etc., ensuring no two wires short together and no complex design rules (like minimum spacing or via spacing) are violated. **Why Routing Matters** - **The RC Delay Bottleneck**: The resistance and capacitance of the long metal routes dominate the timing delay of modern chips. If a critical signal is forced to detour through higher-resistance lower metal layers because the direct route is congested, the chip will fail its operating frequency target. - **Manufacturing Viability**: Violating a single Design Rule Check (DRC) — such as placing two wires 1 nm too close together — means the photomask cannot be legally printed by the foundry. **Advanced Node Challenges** - **Multi-Patterning Constraints**: At 7nm and below, standard lithography cannot print wires close enough. The router must physically assign different "colors" (different photomasks) to adjacent wires, ensuring complex graph-coloring rules are not broken during layout. - **Antenna Rules**: During plasma etching, long metal wires act as antennas, collecting static charge that can literally blow up the fragile transistor gates below. The router must proactively jump up a metal layer and back down (a "diode insertion" or "jumper") to break the antenna effect. Physical Design Routing is **the ultimate constrained 3D puzzle of modern engineering** — determining if a design can survive the harsh physical physics of deep-submicron parasitic delay.