physical verification signoff
**Physical Verification Signoff** is the **final checkpoint before tapeout where the complete chip layout is exhaustively checked against all geometric (DRC), connectivity (LVS), and electrical (ERC/PERC) rules** to confirm manufacturing compatibility and functional correctness. A single escaped error risks silicon failure.
**DRC**: Verifies every geometric shape satisfies foundry manufacturing rules — minimum width, space, enclosure, density, antenna rules, and context-dependent rules. Full-chip DRC at 3nm involves 5,000-10,000+ rules and must produce zero violations for tapeout.
**LVS**: Extracts a netlist from layout (recognizing devices from shapes) and compares against schematic. Checks: **device matching** (correct W/L, fin count), **net matching** (all connections present), **floating nodes**, **shorts**, and **opens**. Multi-billion-transistor LVS involves enormous netlist comparison.
**ERC**: Checks electrical violations: **well/substrate ties** (every N-well needs N+ tie to VDD for latch-up prevention), **gate oxide protection** (no thin oxide directly to I/O pad without ESD), **level shifter checks** (proper voltage domain crossing), and **antenna violations** (long metal during fabrication charges thin gates — requires diode insertion).
**PERC**: Advanced checks: **multi-domain verification** (correct power connectivity and isolation), **ESD path verification** (valid discharge path for every I/O), **back-to-back diode/latch-up detection**, and **voltage stress** (every oxide within reliability limits across power states).
**Signoff Flow**: DRC clean, LVS clean, ERC clean, PERC clean, density checks (all layers within min/max for CMP), and fill verification. Each check takes 12-48+ hours on distributed compute. Incremental verification accelerates debug iterations.
**Physical verification signoff is the contract between design team and foundry that the layout can be manufactured — any escaped violation risks millions in silicon respins.**