place and route pnr

**Place-and-Route (PnR)** is the **core physical design EDA flow that takes a gate-level netlist and transforms it into a manufacturable chip layout — automatically placing millions of standard cells into legal positions on the floorplan and routing all signal and clock connections through the metal interconnect layers, while simultaneously optimizing for timing closure, power consumption, signal integrity, and routability within the constraints of the target technology's design rules**. **PnR Flow Steps** 1. **Floorplanning**: Define the chip outline, place hard macros (memories, analog blocks, I/O cells), and establish power domain boundaries. The floorplan determines the physical context for all subsequent steps. 2. **Placement**: - **Global Placement**: Cells are distributed across the die area using analytical algorithms (quadratic wirelength minimization) that minimize total interconnect length while respecting density constraints. Produces an initial, overlapping placement. - **Legalization**: Cells are snapped to legal row positions (aligned to the placement grid, non-overlapping, within the correct power domain). Minimizes displacement from global placement positions. - **Detailed Placement**: Local optimization swaps neighboring cells to improve timing, reduce wirelength, and fix congestion hotspots. 3. **Clock Tree Synthesis**: Build the clock distribution network (described separately). 4. **Routing**: - **Global Routing**: Determines the approximate path for each net through a coarse routing grid. Balances congestion across the chip — routes are spread to avoid overloading any metal layer or region. - **Track Assignment**: Assigns each route segment to a specific metal track within its global routing tile. - **Detailed Routing**: Determines the exact geometric shape (width, spacing, via locations) of every wire segment, obeying all metal-layer design rules (minimum width, spacing, via enclosure, double-patterning coloring). 5. **Post-Route Optimization**: Timing-driven optimization inserts buffers, resizes gates, and reroutes critical paths to close timing. ECO (Engineering Change Order) iterations fix remaining violations. **Optimization Engines** - **Timing-Driven**: Placement and routing prioritize timing-critical paths. Critical cells are placed closer together; critical nets are routed on faster (wider, lower) metal layers with fewer vias. - **Congestion-Driven**: The tool monitors routing resource utilization per region. Congested areas cause cells to spread, reducing local wire density to prevent DRC violations and unroutable regions. - **Power-Driven**: Gate sizing optimization trades speed for power — cells on non-critical paths are downsized (smaller, lower-power variants) while maintaining timing closure. **Scale of Modern PnR** A modern SoC contains 10-50 billion transistors, 100-500 million standard cell instances, and 200-500 million nets routed across 12-16 metal layers. PnR runtime: 2-7 days on a high-end compute cluster with 500+ CPU cores and 2-4 TB of RAM. Place-and-Route is **the engine that transforms logic into geometry** — converting abstract circuit connectivity into the physical metal patterns that, when manufactured, become a functioning chip.