Planar Ic Junction Isolation Step 01 Confront the Crosstalk Problem
# Confront the Crosstalk Problem Created by Putting More Than One Device on a Single Substrate
## 1. Why Sharing Silicon Is Not Free the Moment a Second Device Is Added
The instant a second transistor is diffused into the same piece of silicon as the first, every device on that chip is electrically connected to every other device through the bulk semiconductor itself, unless something is done to break that connection — a mesa-isolated device from earlier in this project's history never had to confront this problem because each device sat on its own separate die. A bare, undoped or lightly doped substrate conducts, however poorly; two collector regions diffused into the same wafer are two n-type islands separated only by ordinary bulk silicon, and that silicon will carry leakage current between them, couple their signals capacitively, and let one device's switching transient appear as noise on its neighbor, in proportion to how little resistance and reactance the shared bulk actually presents between the two regions:
where $V_A$ and $V_B$ are the two devices' local potentials, $R_{\text{bulk}}$ is the resistance of the shared-substrate path between them, $\rho$ is the substrate resistivity, $d$ the separation, and $A$ the effective cross-section of the conduction path. A single device on its own die never had to pay this term at all; a chip carrying several devices pays it on every pair of neighbors, growing combinatorially with device count unless some isolation mechanism intervenes between every pair.
## 2. Real Diagram: The Two Failure Channels This Sharing Opens, Not Just One
Sharing a substrate opens two distinct channels of interference, not one: a low-frequency, resistive leakage path that lets steady currents and slow signals bleed from one device's region into another's, and a capacitive coupling path, present even where bulk resistance is high, that lets a fast voltage transient on one device induce a transient on its neighbor through the displacement current across the shared silicon.
## 3. Why This Series Treats Isolation as a First-Class Architectural Decision
This project's earlier series spent two generations of fabrication technique, mesa and planar, solving problems specific to a single device sitting alone on a chip: an exposed junction, an etched trench, a mask-aligned contact window. None of that work told a designer what to do the moment a second device needed to sit beside the first inside one function. This series treats that moment as the beginning of a distinct architectural question — not a fabrication detail of one device, but a property a chip-level design has to choose and defend: what separates every pair of devices, how reliably, and at what continuing cost.
Step 1 does not yet choose that mechanism; it names the problem precisely enough that Step 2's specific answer, a reverse-biased junction, can be judged against real alternatives rather than assumed to be the only option.