Planar Ic Junction Isolation Step 04 Define the Isolated Island

# Define the Isolated Island as the Unit a Layout Is Built From, Not the Individual Device

## 1. Why Layout Had to Change Its Unit of Thought Once Isolation Became Architecture

Once Step 3's isolation grid exists, the smallest unit a circuit designer places on the chip is no longer a transistor, a resistor, or a diode by itself; it is an isolated island, a fully enclosed cell of silicon that may contain one device or several, surrounded on every side by isolation diffusion, and every component this layout needs must be assigned to some island before it can be placed at all. This reframes the layout problem this project's own `micrologic_1960` series first confronted at its own Step 1 — designing a layout, not a schematic — in architectural terms general enough to apply beyond any one product: a schematic names components and the connections between them; a layout must additionally decide, for every component, which isolated island it lives in, because two components in the same island share a substrate connection whether the schematic calls for it or not:

$$\text{Island}(k) = \{c_i : c_i \text{ shares isolation boundary } k\}, \qquad \bigcup_k \text{Island}(k) = \text{all components}$$

where every component $c_i$ belongs to exactly one island, and no component may belong to two, because an island's entire purpose is to be the layout's smallest electrically separable region.

From Component to Island, the Layout's New Unit of Thought every component must be assigned to an island before placement means anything SCHEMATIC VIEW components and connections only LAYOUT VIEW island A, two components island B, one component island of k equals the set of components sharing isolation boundary k a schematic says nothing about this; a layout must decide it for every component

## 2. Real Diagram: Two Legitimate Reasons to Group Components Into One Island

A layout designer groups several components into one shared island deliberately, usually for one of two reasons: the components are meant to share a substrate connection anyway (several transistors with a common collector tie), or placing them in one island simply saves the die area an additional isolation boundary between them would cost — a tradeoff this series returns to directly in its area-overhead steps.

Two Reasons to Share an Island Instead of Splitting It intentional shared connection, or simple area economy SHARED CONNECTION BY DESIGN common collector tie intended by the schematic AREA ECONOMY, NOT ELECTRICAL NEED one isolation boundary saved versus splitting the pair both are valid layout choices; both must be made deliberately, never left implicit

## 3. Why This Step Belongs Before Any Cost or Reliability Discussion

Every step after this one in the series — the bias discipline isolation requires, the capacitance it imposes, the area it costs, the parasitic structures it can create between neighbors — is a property of an island or a boundary between islands, not of a device in isolation. Defining the island as the unit a layout is built from, here, gives the rest of this series a vocabulary: when a later step says a boundary must stay reverse-biased, or that a boundary carries capacitance, or that two islands' parasitic paths can turn on together, it is this unit, established now, that each of those claims is about.

Step 4 does not add a new fabrication operation; it names, precisely, the structural unit the rest of this series' claims are claims about.

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