Planar Ic Junction Isolation Step 14 Leakage Current Rises with Heat

# Watch Isolation Leakage Current Rise Sharply as Operating Temperature Climbs

## 1. Why the Reverse Saturation Current Step 2 Called Small Is Not Fixed

Step 2 treated the isolation junction's reverse saturation current $I_0$ as small enough to ignore, and at room temperature, for a well-made junction, it generally is; but $I_0$ is not a fixed property of the junction, it is a strongly temperature-dependent quantity, roughly doubling for every 8 to 10 degrees Celsius of temperature rise for silicon, because reverse saturation current is dominated by minority-carrier generation, a thermally activated process that accelerates sharply as temperature climbs. An isolation junction judged adequate at room temperature can carry a reverse leakage current orders of magnitude larger at the elevated temperatures a real package reaches under load or in a hot environment, directly eroding the margin Step 2's entire isolation argument depended on:

$$I_0(T) \propto T^3 \, e^{-E_g/kT}, \qquad I_0(T_2) \approx I_0(T_1) \cdot 2^{(T_2-T_1)/10}$$

where $E_g$ is silicon's bandgap energy and the empirical doubling rule on the right is the practical consequence circuit designers actually have to plan around — a junction that isolates comfortably at 25 degrees Celsius can be carrying far less margin, or none, at 125 degrees Celsius.

Leakage That Was Negligible at Room Temperature, Climbing reverse saturation current roughly doubles every 8 to 10 degrees celsius temperature I0 25 C, negligible 125 C, far larger I0 of T proportional to T cubed times e to the minus E g over kT, doubling roughly every 10 C a margin judged safe at room temperature is not automatically safe hot

## 2. Real Diagram: Every Downstream Cost This Series Named Gets Worse Together, Hot

Rising leakage current at high temperature does not act alone; it compounds with the capacitive crosstalk Step 9 described (both are symptoms of a weakening isolation barrier) and with the parasitic four-layer structure Step 12 identified, since higher leakage current is exactly the kind of stray current that can supply the triggering injection a dormant parasitic thyristor needs to turn on.

Heat Compounds Every Isolation Weakness Named So Far rising leakage is not an isolated cost; it feeds the risks steps 9 and 12 already named rising leakage, this step crosstalk margin, step 9 parasitic trigger risk, step 12 a thermal derating policy has to account for all three together, not leakage alone

## 3. Why Temperature Is Not a Separate Topic From Everything Else This Series Has Named

Every cost this series has quantified so far — leakage, capacitance, area, parasitic triggering — was described at an implicit reference temperature; this step makes explicit that none of those numbers are fixed across the operating range a real product has to survive, and that a design margin computed at room temperature can silently evaporate at the high end of a part's rated temperature range. This is why Step 15 follows immediately with the temperature range question this step's physics actually forces: how hot can this architecture run before its own isolation ceases to be trustworthy at all.

Step 14 shows that every isolation cost this series has named gets measurably worse as temperature rises, not just the leakage current most directly responsible.

Take planar ic junction isolation step 14 leakage current rises with heat further

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