Planar Transistor

A planar transistor is a transistor whose junctions are formed through windows in a layer of silicon dioxide and stay covered by that oxide for the life of the device, so the entire structure is a flat, protected sandwich with metal contacts reaching down through small openings. Jean Hoerni developed the idea at Fairchild Semiconductor in 1957 to 1959, and Fairchild's 2N1613 of 1960 was among the first planar silicon transistors sold. Where the planar process is the manufacturing recipe, the planar transistor is the device that recipe produced, and its defining feature is not that it is flat but that no p-n junction is ever left naked at the surface: each one comes up under oxide.

The planar transistor answered the mesa transistor's central weakness, the exposed junction. In a mesa device the etch cut through the collector-base junction and left it open on the sidewall, where contamination could raise leakage and drift. In a planar device, a thermally grown oxide covers the wafer, the base is diffused through one window and the emitter through a smaller window inside it, and each junction curves up to the surface beneath the oxide rather than being cut open. Silicon dioxide is a stable, hard, electrically insulating glass that excludes most moisture and ions, and the silicon-oxide interface, studied by Mohamed Atalla and others at Bell Labs in the late 1950s, was found to carry far fewer harmful surface states than any earlier surface treatment.

Hoerni's work, and the 2N1613 as its first widely known product, turned the design from a laboratory result into a manufacturing standard. Hoerni recorded his planar ideas in notebook entries in December 1957 and January 1959, and Fairchild applied for a patent on the process in 1959. The 2N1613 came in 1960 as a planar silicon n-p-n transistor in a metal can, delivering the kind of low leakage and stable gain that mesa devices struggled to hold, and variants of this type continued in production for decades. The process also coexisted with Frosch and Derick's 1957 oxide masking discovery at Bell Labs and with photolithography of the kind demonstrated by Lathrop and Nall in 1957 and 1958, since the planar method needs both.

The flat, oxide-covered surface did more than protect the junctions: it made integration possible. Because the contacts sit on top of an insulating layer, a thin aluminium line can run from one device to another across the oxide without shorting to the silicon, which is the insight that Robert Noyce took up in 1959 when he proposed planar interconnection for the integrated circuit. Without that surface, joining multiple transistors on one chip would have meant wires or air bridges for every connection. Planar manufacturing also helped the economics: dozens or hundreds of transistors are made together on one wafer, and a single set of photomasks reproduces identical devices, which is the foundation of why transistors fell in price so quickly in the 1960s.

Two common misconceptions are worth correcting. One is that planar means two-dimensional; it simply means the junctions and contacts are on one flat surface rather than raised on a plateau, and the devices still have depth. The other is that planar technology eliminated surface problems; the oxide-silicon interface still carries trapped charge and mobile ions, and sodium contamination in particular caused instability in early MOS and bipolar devices until cleaning and gettering methods improved. The planar approach also still has a modest cost, because the oxide must be grown, patterned and re-grown, and every step demands clean room discipline. In modern CMOS, the transistor is still planar in the structural sense in many older generations, while newer finFET and gate-all-around structures leave the planar form to gain electrical control.

Read planar transistor as a transistor built flat under glass, a device in which every junction stays protected and every wire can run over the top.