plasma etch process semiconductor

**Plasma Etch Process Engineering** is the **CMOS manufacturing discipline that uses reactive gas plasmas to transfer lithographic patterns into underlying materials with nanometer precision — where the etch must simultaneously achieve the target feature dimensions (CD), vertical sidewall profiles (>88°), high selectivity to masking and underlying layers (>10:1 to >100:1), and no damage to sensitive device structures, making plasma etch the pattern transfer workhorse that is used 30-50 times per chip at advanced nodes for every critical feature from transistor fins to metal interconnects**. **Plasma Etch Fundamentals** A low-pressure gas discharge (plasma) generates reactive species: - **Radicals**: Chemically reactive neutral species (F, Cl, O radicals) that etch by chemical reaction with the substrate surface. - **Ions**: Positively charged species (Ar⁺, CF₃⁺, Cl₂⁺) accelerated by the substrate bias voltage. Provide directional (anisotropic) etch by bombarding the surface vertically. - **Etch Mechanism**: Ion-enhanced chemical etching — ions provide energy and directionality, radicals provide the chemical reaction. Vertical surfaces receive ion bombardment; horizontal surfaces are protected by sidewall passivation polymer (deposited from etch byproducts). **Etch Types and Chemistries** - **Silicon Etch**: SF₆/C₄F₈ (Bosch process for deep etch), HBr/Cl₂/O₂ (gate etch, fin etch). HBr produces SiBr₄ volatile product + sidewall passivation from SiOxBry. - **Oxide (SiO₂) Etch**: C₄F₈/CF₄/CHF₃/Ar. Fluorocarbon radicals react with SiO₂ to form SiF₄ + CO/CO₂ (volatile). C₄F₈ provides polymerization for high-AR contact/via etch with sidewall protection. - **Nitride (Si₃N₄) Etch**: CH₂F₂/CHF₃/O₂. Adding hydrogen scavenges F radicals, reducing SiO₂ etch rate while maintaining Si₃N₄ etch → achieves N₃N₄-to-SiO₂ selectivity >10:1. - **Metal (W, Cu barrier) Etch**: SF₆/Cl₂ for W. Ar ion milling for Cu barrier (Ta/TaN). Cu itself is not plasma-etched (no volatile Cu halides at room temperature). - **Organic (Resist, Hardmask) Etch**: O₂, CO₂, N₂/H₂ ash. Oxidizes carbon-containing materials. Used for resist strip and organic hardmask etch. **Critical Etch Applications** - **Fin Etch (FinFET/GAA)**: Etch Si fins with <1 nm CD uniformity across the wafer. Fin width: 5-7 nm. Fin height: 40-50 nm. Profile: perfectly vertical. Selectivity to STI SiO₂ at fin base: >30:1. - **Gate Etch**: Etch metal gate (TiN/W) stack with <0.5 nm CD variation. Stop on ultra-thin high-k (1.5 nm HfO₂) without punching through to the channel. - **Contact/Via Etch**: High-AR etch through ILD to reach S/D contacts. AR: 10-20:1 at advanced nodes. Etch stop on silicide (TiSi) or metal (W/Co). Circular hole profile must be maintained — no bowing, twisting, or bottom CD closure. - **3D NAND Channel Hole Etch**: The most extreme HAR etch in semiconductor manufacturing. AR: 60-100:1. Depth: 5-15 μm. Requires pulsed plasma, mixed-mode chemistry, and multi-step recipes. **Advanced Etch Techniques** - **Atomic Layer Etch (ALE)**: Self-limiting etch that removes exactly one atomic layer per cycle (analogous to ALD for deposition). Enables atomic-precision depth control and surface smoothing. Used for fin trimming (sub-nm CD control) and gate recess. - **Quasi-ALE**: Alternating deposition and etch steps with partial self-limitation. Practical compromise between throughput and precision. - **Cryogenic Etch**: Wafer cooled to -80 to -120°C. Reduced chemical etch rate improves profile control and selectivity for certain materials (Si etch with SF₆/O₂). Plasma Etch is **the sculptor of semiconductor features** — the process that carves nanometer-scale patterns into silicon, metal, and dielectric with the precision, directionality, and selectivity required to build transistors and interconnects at the atomic scale, making etch engineering one of the most demanding and impactful specialties in semiconductor manufacturing.