pll jitter
**PLL Jitter and Phase Noise** is the **characterization of timing uncertainty in the clock signal generated by phase-locked loops** — measuring the short-term random variations in clock edge placement that directly determine the maximum achievable frequency for synchronous digital circuits and the signal quality for RF/communication systems.
**What Is Jitter?**
- **Jitter**: Random variation in the timing of clock edges relative to their ideal positions.
- **Period Jitter**: Variation in clock period from cycle to cycle.
- **Long-Term Jitter**: Accumulated timing error over many cycles.
- **Cycle-to-Cycle Jitter**: Difference in period between two consecutive cycles.
**Jitter Sources in PLLs**
| Source | Type | Magnitude |
|--------|------|----------|
| VCO phase noise | Random | Dominant source (thermal noise in oscillator) |
| Charge pump mismatch | Deterministic | Causes reference spurs |
| Power supply noise | Both | Vdd ripple modulates VCO frequency |
| Input reference jitter | Random/Det. | Passes through PLL bandwidth |
| Divider noise | Random | Thermal noise in frequency divider |
**Phase Noise (Frequency Domain View)**
- Phase noise: $L(f) = 10 \log_{10}\left(\frac{P_{noise}(f)}{P_{carrier}}\right)$ in dBc/Hz.
- Plotted as noise power spectral density vs. offset frequency from carrier.
- **Inside PLL bandwidth**: Reference noise dominates (PLL tracks reference).
- **Outside PLL bandwidth**: VCO free-running noise dominates (PLL can't correct fast variations).
**Jitter Budget in Digital Design**
- Available timing margin = Clock period - Setup time - Hold time.
- Jitter consumes part of this margin:
- Total jitter budget = Deterministic jitter (DJ) + Random jitter (RJ, at target BER).
- $TJ = DJ + 2 \times N \times RJ_{rms}$ where N = 6–7 for BER = 10⁻¹².
- **Example**: At 5 GHz (200 ps period), if setup+hold = 100 ps → only 100 ps margin → jitter must be < 20-30 ps total.
**PLL Types and Jitter Performance**
| PLL Type | Jitter (rms) | Application |
|----------|-------------|-------------|
| LC PLL | 0.1-1 ps | High-speed SerDes (PCIe, DDR) |
| Ring PLL | 1-10 ps | General digital clocking |
| All-Digital PLL (ADPLL) | 0.5-5 ps | SoC integration (no analog components) |
| Fractional-N PLL | 0.2-2 ps | RF frequency synthesis |
**Jitter Measurement**
- **Oscilloscope**: Time-domain histogram of clock period — direct jitter measurement.
- **Spectrum Analyzer**: Measure phase noise L(f) — convert to integrated jitter.
- **On-Chip**: DLL-based jitter measurement circuits or time-to-digital converters (TDC).
PLL jitter is **a fundamental limit on digital system performance** — at multi-GHz clock frequencies, every picosecond of jitter directly reduces the timing window available for useful computation, making PLL design quality a critical determinant of chip maximum frequency.